Method of forming a single metal that performs N work function and P work function in a high-k/metal gate process

• US 9,960,160 B2
• Filed: 08/29/2013
• Issued: 05/01/2018
• Est. Priority Date: 08/18/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yih-Ann, Chen, Ryan Chia-Jen, Chao, Donald Y., Mor, Yi-Shien, Huang, Kuo-Tai
• Primary Examiner(s): Jahan, Bilkis
• Application Number:
  US14/013,960
• Publication Number:
  US 20140001566A1
• Time in Patent Office: 1,706 Days
• Field of Search: 257369
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

The present disclosure describes a semiconductor device. The device includes a semiconductor substrate, an isolation structure formed in the substrate for isolating a first active region and a second active region, a first transistor formed in the first active region, the first transistor having a high-k gate dielectric layer and a metal gate with a first work function formed over the high-k gate dielectric layer, and a second transistor formed in the second active region, the second transistor having the high-k gate dielectric layer and a metal gate with a second work function formed over the high-k gate dielectric layer. The metal gates are formed from at least a single metal layer having the first work function and the second work function.

Claims

1. A semiconductor device comprising:

a silicon substrate;

an isolation structure formed in the silicon substrate for isolating a first active region and a second active region;

a first transistor formed in the first active region, the first transistor having an interfacial layer, a capping layer over the interfacial layer, a high-k gate dielectric layer over the capping layer, and a metal gate with a first work function formed over the high-k gate dielectric layer, wherein the metal gate with the first work function is formed from a first portion of a metal nitride layer, the first portion of the metal nitride layer having a first chemical composition XN, where X denotes a transition metal; and

a second transistor formed in the second active region, the second transistor having the interfacial layer, the capping layer over the interfacial layer, the high-k gate dielectric layer over the capping layer, and a metal gate with a second work function formed over the high-k gate dielectric layer, wherein the metal gate with the second work function is formed from a second portion of the metal nitride layer, the second portion of the metal nitride layer having a second chemical composition XAlN.

2. The semiconductor device of claim 1, wherein the first work function is an N-metal work function and wherein the second work function is a P-metal work function.

3. The semiconductor device of claim 1, wherein the second portion of the metal nitride layer is prepared by treating the second portion with an Al implantation process.

4. The semiconductor device of claim 1, wherein the transition metal includes one of Ti and Ta.

5. The semiconductor device of claim 1, wherein the high-k gate dielectric layer includes one of hafnium oxide (HfO₂), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), and combinations thereof.

6. The semiconductor device of claim 1, wherein the interfacial layer does not physically contact the isolation structure.

7. A semiconductor device comprising:

a silicon substrate;

an isolation structure formed in the silicon substrate for isolating a first active region and a second active region;

a first transistor formed in the first active region, the first transistor having an interfacial layer, a high-k gate dielectric layer over the interfacial layer, a metal gate with a first work function formed over the high-k gate dielectric layer, and a poly layer formed over the metal gate with the first work function, wherein the metal gate with the first work function comprises a first composition comprising Ti, N, and Al; and

a second transistor formed in the second active region, the second transistor having the interfacial layer, the high-k gate dielectric layer over the interfacial layer, a metal gate with a second work function formed over the high-k gate dielectric layer, and a poly layer over the metal gate with the second work function, wherein the metal gate with the second work function comprises a second composition comprising Ti, N, and Al, the second composition being different from the first composition.

8. The semiconductor device of claim 7, wherein the first work function is an N-metal work function and wherein the second work function is a P-metal work function.

9. The semiconductor device of claim 7, wherein the first composition comprises 30% of N and 17.5% of Al and the second composition comprises 50% of N and 12.5% of Al.

10. The semiconductor device of claim 7, wherein the high-k gate dielectric layer includes one of hafnium oxide (HfO₂), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), and combinations thereof.

11. The semiconductor device of claim 7, further comprising a first capping layer formed over or under the high-k gate dielectric layer in the first transistor, and a second capping layer formed over or under the high-k gate dielectric layer in the second transistor.

12. The semiconductor device of claim 11, wherein the first capping layer and the second capping layer each includes one of lanthanum oxide and aluminum oxide.

13. The semiconductor device of claim 11, wherein the first capping layer is between the interfacial layer and the high-k gate dielectric layer in the first transistor, wherein the second capping layer is between the interfacial layer and the high-k gate dielectric layer in the second transistor.