Hybrid high-k first and high-k last replacement gate process

• US 9,960,162 B2
• Filed: 06/16/2016
• Issued: 05/01/2018
• Est. Priority Date: 12/29/2013
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Niimi, Hiroaki, Mehrotra, Manoj, Nandakumar, Mahalingam
• Primary Examiner(s): Hossain, Moazzam
• Assistant Examiner(s): Lu, Farun
• Application Number:
  US15/184,405
• Publication Number:
  US 20160300836A1
• Time in Patent Office: 684 Days
• CPC Class Codes: H01L 21/02148 the material containing hafnium, e.g. HfSiOx or HfSiON
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02332 into an oxide layer, e.g. changing SiO to SiON
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/0271 comprising organic layers
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/823828 : with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 : gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 : with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 : Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/42364 : characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42372 : characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 : the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

Claims

1. A process of forming an integrated circuit, comprising the steps:

providing a partially processed wafer of the integrated circuit;

growing a first gate dielectric on the partially processed wafer at a temperature of 850°

C. or greater;

depositing a high-k first gate dielectric on the first gate dielectric;

forming an NMOS polysilicon replacement gate of an NMOS transistor on the high-k first gate dielectric;

forming a PMOS polysilicon replacement gate of a PMOS transistor on the high-k first gate dielectric;

depositing a premetal dielectric over the NMOS transistor and over the PMOS transistor;

planarizing the premetal dielectric to expose a top of the PMOS polysilicon replacement gate and a top of the NMOS polysilicon replacement gate;

removing the NMOS polysilicon replacement gate forming an NMOS replacement gate trench;

removing the PMOS polysilicon replacement gate forming a PMOS replacement gate trench;

forming an NMOS transistor photo resist pattern wherein the NMOS transistor photo resist pattern covers the NMOS replacement gate trench and exposes the PMOS replacement gate trench;

removing the high-k first gate dielectric and removing the first gate dielectric from a bottom of the PMOS replacement gate trench;

removing the NMOS transistor photo resist pattern;

after removing the NMOS transistor photo resist pattern, forming a second gate dielectric on the integrated circuit wherein the second gate dielectric covers the bottom of the PMOS replacement gate trench;

depositing a high-k last gate dielectric on the integrated circuit including in the PMOS replacement gate trench and in the NMOS replacement gate trench;

depositing PMOS metal gate material;

forming a PMOS transistor photo resist pattern wherein the PMOS photo resist pattern covers the PMOS transistor and exposes the NMOS transistor;

etching the PMOS metal gate material from the NMOS transistor including from within the NMOS replacement gate trench;

etching the high-k last gate dielectric from the NMOS transistor including from within the NMOS replacement gate trench;

depositing NMOS metal gate material on the integrated circuit and into the NMOS replacement gate trench; and

polishing the integrated circuit to remove the NMOS and the PMOS metal gate material from a surface of the premetal dielectric and to form an NMOS metal gate in the NMOS replacement gate trench and to form a PMOS metal gate in the PMOS replacement gate trench.

2. The process of claim 1, wherein the high-k first gate dielectric is HfO_x, wherein the high-k last gate dielectric is HfSiON, and wherein the step of etching the high-k last gate dielectric comprises etching the high-k last gate dielectric using 1000:

1 HF at a temperature of about 80°

C.

3. The process of claim 1, wherein the high-k first gate dielectric is HfO_x, wherein the high-k last gate dielectric is ZrO₂, and wherein the step of etching the high-k last gate dielectric comprises etching the high-k last gate dielectric using 1000:

1 HF at a temperature of about 80°

C.

4. The process of claim 1, wherein the first gate dielectric is silicon dioxide with a thickness in the range of 0.5 to 1.5 nm and wherein the second gate dielectric is an oxide chemically grown in SC1 to a thickness of about 0.6 nm.

5. The process of claim 1, wherein the high-k first gate dielectric is selected from the group consisting of HfO_x, HfSiO_x, HfSiON, ZrO₂, HfZrO_x, AlO_x, or TiO_x and wherein the high-k last gate dielectric is selected from the group consisting of HfO_x, HfSiO_x, HfSiON, ZrO₂, HfZrO_x, AlO_x, or TiO_x.

6. The process of claim 3, wherein the NMOS metal gate material is selected from the group consisting of titanium, aluminum, titanium-aluminum alloy, and tungsten and wherein the PMOS metal gate material is selected from the group consisting of titanium nitride, tantalum nitride, aluminum, and platinum.

7. The process of claim 3, wherein

the gate dielectric is nitrided silicon dioxide with a thickness in the range of about 0.5 to 1.5 nm;

the high-k first gate dielectric is HfO_x with a thickness in the range of about 1 to 3 nm;

the NMOS metal gate material is titanium-aluminum alloy with a thickness of about 3 nm;

the second gate dielectric is chemically grown with SC1 with a thickness of about 0.6 nm

the high-k last gate dielectric is HfSiON or ZrO₂ with a thickness in the range of about 1 to 3 nm; and

the PMOS metal gate material is titanium nitride with a thickness in the range of about 8 nm.

8. A process of forming an integrated circuit, comprising the steps:

growing a first gate dielectric on a substrate;

depositing a high-k first gate dielectric on the first gate dielectric;

forming a first polysilicon replacement gate and a second polysilicon replacement gate on the high-k first gate dielectric;

depositing a premetal dielectric over the substrate;

planarizing the premetal dielectric to expose the first polysilicon replacement gate and the second polysilicon replacement gate;

removing the first polysilicon replacement gate forming a first gate trench;

removing the second polysilicon replacement gate forming a second gate trench;

removing the high-k first gate dielectric and the first gate dielectric from the second gate trench but not the first gate trench;

forming a second gate dielectric over the substrate including in the second gate trench;

depositing a high-k last gate dielectric on the substrate including in both the first gate trench and the second gate trench;

depositing PMOS metal gate material including in the first gate trench and the second gate trench;

etching the PMOS metal gate material from the first gate trench;

etching the high-k last gate dielectric layer from the first gate trench;

depositing NMOS metal gate material over the substrate and into the first gate trench but not the second gate trench; and

polishing the integrated circuit to remove the NMOS and the PMOS metal gate material from a surface of the premetal dielectric and to form an NMOS metal gate in the first gate trench and to form a PMOS metal gate in the second gate trench.

9. The process of claim 8, wherein the high-k first gate dielectric is HfO_x.

10. The process of claim 8, wherein the high-k last gate dielectric is HfSiON.

11. The process of claim 8, wherein the step of etching the high-k last gate dielectric comprises etching the high-k last gate dielectric using 1000:

1 HF at a temperature of about 80°

C.

12. The process of claim 8, wherein the high-k last gate dielectric is ZrO₂.

13. The process of claim 8, wherein the first gate dielectric is silicon dioxide with a thickness in the range of 0.5 to 1.5 nm and wherein the second gate dielectric is an oxide chemically grown in SC1 to a thickness of about 0.6 nm.

14. The process of claim 8, wherein the high-k first gate dielectric is selected from the group consisting of HfO_x, HfSiO_x, HfSiON, ZrO₂, HfZrO_x, AlO_x, or TiO_x and wherein the high-k last gate dielectric is selected from the group consisting of HfO_x, HfSiO_x, HfSiON, ZrO₂, HfZrO_x, AlO_x, or TiO_x.

15. The process of claim 14, wherein the NMOS metal gate material is selected from the group consisting of titanium, aluminum, titanium-aluminum alloy, and tungsten and wherein the PMOS metal gate material is selected from the group consisting of titanium nitride, tantalum nitride, aluminum, and platinum.

16. The process of claim 14, wherein

the first gate dielectric is nitrided silicon dioxide with a thickness in the range of about 0.5 to 1.5 nm;

the high-k first gate dielectric is HfO_x with a thickness in the range of about 1 to 3 nm;

the NMOS metal gate material is titanium-aluminum alloy with a thickness of about 3 nm;

the second gate dielectric is chemically grown with SC1 with a thickness of about 0.6 nm

the high-k last gate dielectric is HfSiON or ZrO₂ with a thickness in the range of about 1 to 3 nm; and

the PMOS metal gate material is titanium nitride with a thickness in the range of about 8 nm.

17. A process of forming an integrated circuit, comprising the steps:

growing a first gate dielectric on a partially processed wafer;

depositing a high-k first gate dielectric on the first gate dielectric;

forming an NMOS polysilicon replacement gate of an NMOS transistor on the high-k first gate dielectric;

forming a PMOS polysilicon replacement gate of a PMOS transistor on the high-k first gate dielectric;

depositing a premetal dielectric over the NMOS transistor and over the PMOS transistor;

planarizing the premetal dielectric to expose a top of the PMOS polysilicon replacement gate and a top of the NMOS polysilicon replacement gate;

removing the NMOS polysilicon replacement gate forming an NMOS replacement gate trench;

removing the PMOS polysilicon replacement gate forming a PMOS replacement gate trench;

after removing the NMOS polysilicon replacement gate and the PMOS polysilicon replacement gate, forming an NMOS transistor photo resist pattern wherein the NMOS transistor photo resist pattern covers the NMOS replacement gate trench and exposes the PMOS replacement gate trench;

removing the high-k first gate dielectric and removing the first gate dielectric from a bottom of the PMOS replacement gate trench;

removing the NMOS transistor photo resist pattern;

forming a second gate dielectric on the integrated circuit wherein the second gate dielectric covers the bottom of the PMOS replacement gate trench;

depositing a high-k last gate dielectric on the integrated circuit including in the PMOS replacement gate trench and in the NMOS replacement gate trench;

depositing PMOS metal gate material;

forming a PMOS transistor photo resist pattern wherein the PMOS photo resist pattern covers the PMOS transistor and exposes the NMOS transistor;

etching the PMOS metal gate material from the NMOS transistor including from within the NMOS replacement gate trench;

etching the high-k last gate dielectric from the NMOS transistor including from within the NMOS replacement gate trench;

depositing NMOS metal gate material on the integrated circuit and into the NMOS replacement gate trench; and

polishing the integrated circuit to remove the NMOS and the PMOS metal gate material from a surface of the premetal dielectric and to form an NMOS metal gate in the NMOS replacement gate trench and to form a PMOS metal gate in the PMOS replacement gate trench.

18. The process of claim 17, wherein the high-k first gate dielectric is HfO_x and the high-k last gate dielectric is HfSiON.

19. The process of claim 17, wherein the high-k first gate dielectric is HfO_x and the high-k last gate dielectric is ZrO₂.

20. The process of claim 17, wherein the first gate dielectric is silicon dioxide with a thickness in the range of 0.5 to 1.5 nm and wherein the second gate dielectric is an oxide chemically grown in SC1 to a thickness of about 0.6 nm.