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Method of operating semiconductor memory device with floating body transisor using silicon controlled rectifier principle

  • US 9,960,166 B2
  • Filed: 08/11/2017
  • Issued: 05/01/2018
  • Est. Priority Date: 08/05/2008
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • an array of semiconductor memory cells comprising at least two semiconductor memory cells, wherein each said semiconductor memory cell includes;

    a transistor comprising a source region, a first floating body region, a drain region, and a gate, and a silicon controlled rectifier device having a cathode region, a second floating body region, a buried layer region, and an anode region,wherein;

    a state of said memory cell is stored in said first floating body region,said first floating body region and said second floating body region are common,said silicon controlled rectifier device maintains a state of said memory cell,said transistor is usable to access said memory cell, andwherein said anode region is commonly connected to at least two of said memory cells; and

    a control circuit configured to provide electrical signals to said anode region, wherein when a first memory cell of said at least two of said memory cells is in a first state and a second memory cell of said at least two of said memory cells is in a second state, application of electrical signals via said control circuit maintains said first memory cell in said first state and said second memory cell in said second state.

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