Semiconductor devices, power semiconductor devices, and methods for forming a semiconductor device

• US 9,960,268 B2
• Filed: 10/07/2016
• Issued: 05/01/2018
• Est. Priority Date: 10/15/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Zundel, Markus, Kampen, Christian, Ludwig, Jacob Tillmann
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US15/288,243
• Publication Number:
  US 20170110572A1
• Time in Patent Office: 571 Days
• Field of Search: 257285, 257328, 257330, 257332, 257334, 257E2902, 257E29066, 257E29262, 257E2141, 257E21211, 257E21616, 257E2706, 257E27091, 438270, 438495, 438508
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a drift region of a device structure arranged in a semiconductor layer. The drift region includes at least one first drift region portion and at least one second drift region portion. A majority of dopants within the first drift region portion are a first species of dopants having a diffusivity less than a diffusivity of phosphor within the semiconductor layer. Further, a majority of dopants within the second drift region portion are a second species of dopants. Additionally, the semiconductor device includes a trench extending from a surface of the semiconductor layer into the semiconductor layer. A vertical distance of a border between the first drift region portion and the second drift region portion to the surface of the semiconductor layer is larger than 0.5 times a maximal depth of the trench and less than 1.5 times the maximal depth of the trench.

Claims

1. A semiconductor device, comprising:

a drift region of a device structure arranged in a semiconductor layer, wherein the drift region comprises at least one first drift region portion and at least one second drift region portion, wherein a majority of dopants within the at least one first drift region portion are a first species of dopants having a diffusivity less than a diffusivity of phosphor within the semiconductor layer, wherein a majority of dopants within the at least one second drift region portion are a second species of dopants; and

a trench extending from a surface of the semiconductor layer into the semiconductor layer, wherein a vertical distance between the surface of the semiconductor layer and a border between the at least one first drift region portion and the at least one second drift region portion is larger than 0.5 times a maximal depth of the trench and less than 1.5 times the maximal depth of the trench,

wherein the at least one second drift region portion is located between the surface of the semiconductor layer and the at least one first drift region portion.

2. The semiconductor device of claim 1, wherein the device structure is a transistor structure and the trench is a gate trench of the transistor structure, and wherein a gate electrode of the transistor structure is located within the gate trench.

3. The semiconductor device of claim 1, further comprising a body region of the device structure, wherein the body region is located adjacent to the at least one second drift region portion.

4. The semiconductor device of claim 1, wherein a maximal doping concentration within the at least one first drift region portion and the at least one second drift region portion of the drift region is less than 1*10¹⁸ doping atoms per cm³.

5. The semiconductor device of claim 1, wherein an average net doping concentration value of the drift region is at least 1*10¹⁶ doping atoms per cm³.

6. The semiconductor device of claim 1, wherein a local minimum of a net doping concentration of the drift region is located at the border between the at least one first drift region portion and the at least one second drift region portion.

7. The semiconductor device of claim 1, wherein the vertical distance between the surface of the semiconductor layer and the border between the at least one first drift region portion and the at least one second drift region portion is larger than the maximal depth of the trench.

8. The semiconductor device of claim 1, wherein the second species of doping atoms is phosphor.

9. The semiconductor device of claim 1, wherein a vertical extension of the at least one first drift region portion is larger than 1 μ

m.

10. The semiconductor device of claim 1, further comprising a semiconductor substrate located adjacent to the semiconductor layer, wherein a doping concentration at a transition from the drift region to the semiconductor substrate varies between a first doping concentration value and a second doping concentration value over a distance of less than 500 nm, wherein the first doping concentration value is an average net doping concentration of a mid-portion of the drift region plus 20% of the average net doping concentration of the mid-portion of the drift region, wherein the mid-portion of the drift region lies within a middle 50% of a vertical dimension of the drift region, and wherein the second doping concentration value is an average net doping concentration of the mid-portion of the drift region plus one decade.

11. The semiconductor device of claim 10, wherein the doping concentration at the transition from the drift region to the semiconductor substrate increases from the first doping concentration value to the second doping concentration value over a distance of more than 100 nm.

12. The semiconductor device of claim 10, wherein the semiconductor substrate is doped with doping atoms having a diffusivity less than a diffusivity of phosphor within the semiconductor substrate.

13. The semiconductor device of claim 10, wherein the semiconductor layer and the semiconductor substrate are doped with the same doping atoms.

14. The semiconductor device of claim 10, wherein an average net doping concentration of a source or collector region arranged in the semiconductor substrate is at least 1*10¹⁹ doping atoms per cm³.

15. The semiconductor device of claim 1, wherein the semiconductor layer has a thickness of less than 8 μ

m.

16. The semiconductor device of claim 1, wherein the semiconductor layer is an epitaxially grown semiconductor layer.

17. The semiconductor device of claim 1, wherein the device structure of the semiconductor device comprises a breakdown voltage of at least 10 V.

18. A semiconductor device, comprising:

a drift region of a device structure arranged in a semiconductor layer located adjacently to a semiconductor substrate,

wherein a doping concentration at a transition from the drift region to the semiconductor substrate varies between a first doping concentration value and a second doping concentration value over a distance of less than 500 nm,

wherein the first doping concentration value is an average net doping concentration of a mid-portion of the drift region plus 20% of the average net doping concentration of the mid-portion of the drift region,

wherein the mid-portion of the drift region lies within a middle 50% of a vertical dimension of the drift region,

wherein the second doping concentration value is an average net doping concentration of the mid-portion of the drift region plus one decade.

19. The semiconductor device of claim 18, wherein the doping concentration at the transition from the drift region to the semiconductor substrate increases from the first doping concentration value to the second doping concentration value over a distance of more than 100 nm.

20. The semiconductor device of claim 18, wherein the semiconductor substrate is doped with doping atoms having a diffusivity less than a diffusivity of phosphor within the semiconductor substrate.

21. The semiconductor device of claim 18, wherein the semiconductor layer and the semiconductor substrate are doped with the same doping atoms.

22. The semiconductor device of claim 18, wherein an average net doping concentration of a source or collector region arranged in the semiconductor substrate is at least 1*10¹⁹ doping atoms per cm³.

23. A method for forming a semiconductor device, the method comprising:

epitaxially growing a first epitaxial semiconductor sub layer of a semiconductor layer on a semiconductor substrate, wherein a majority of dopants within the first epitaxial semiconductor sub layer are a first species of dopants having a diffusivity less than a diffusivity of phosphor within the semiconductor layer;

epitaxially growing a second epitaxial semiconductor sub layer of a semiconductor layer after forming the first epitaxial semiconductor sub layer, wherein a majority of dopants within the second epitaxial semiconductor sub layer are a second species of dopants; and

forming a trench extending from a surface of the semiconductor layer into the semiconductor layer, wherein a vertical distance of a border between the first epitaxial semiconductor sub layer and the second epitaxial semiconductor sub layer to the surface of the semiconductor layer is larger than 0.5 times a maximal depth of the trench and less than 1.5 times the maximal depth of the trench.