Method of forming vertical field effect transistors with different threshold voltages and the resulting integrated circuit structure

• US 9,960,271 B1
• Filed: 04/18/2017
• Issued: 05/01/2018
• Est. Priority Date: 04/18/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Yeh, Chun-chen, Yamashita, Tenko, Cheng, Kangguo
• Primary Examiner(s): Blum, David S
• Application Number:
  US15/490,255
• Time in Patent Office: 378 Days
• Field of Search: 438268
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

An integrated circuit and method are disclosed. In the method, a stack of sacrificial layers is formed on a semiconductor layer such that a first portion of the stack has an extra sacrificial layer as compared to a second portion. First and second multi-layer fins are etched through the first and second portions and into the semiconductor layer. First and second vertical field effect transistors (VFETs) are formed using the fins. During VFET formation, multiple etch processes are performed to remove the sacrificial layers. The last of these etch processes is a selective isotropic etch process that removes the extra sacrificial layer and etches back first and second upper dielectric spacers on the first and second multi-layer fins. Due to the extra sacrificial layer, the first upper dielectric spacer will be taller than the second and the first VFET will have a higher threshold voltage than the second.

Claims

1. A method comprising:

forming a stack of sacrificial layers on a semiconductor layer, the stack having a first portion and a second portion, the first portion comprising an extra sacrificial layer as compared to the second portion;

etching a first multi-layer fin in the first portion and the semiconductor layer and a second multi-layer fin in the second portion and the semiconductor layer; and

concurrently forming a first vertical field effect transistor using the first multi-layer fin and a second vertical field effect transistor using the second multi-layer fin, the concurrently forming comprising;

forming a first upper dielectric spacer on the first multi-layer fin and a second upper dielectric spacer on the second multi-layer fin; and

performing multiple etch processes that remove the sacrificial layers from the first multi-layer fin and the second multi-layer fin, wherein the multiple etch processes comprise;

initial etch processes that remove all of the sacrificial layers except the extra sacrificial layer on the first multi-layer fin; and

an isotropic etch process that removes the extra sacrificial layer from the first multi-layer fin and etches back the first upper dielectric spacer and the second upper dielectric spacer,

wherein, during the isotropic etch process, the first upper dielectric spacer is partially protected by the extra sacrificial layer until the extra sacrificial layer is removed such that the second upper dielectric spacer is etched back faster than the first upper dielectric spacer and such that, following the isotropic etch process, the first upper dielectric spacer is taller than the second upper dielectric spacer.

2. The method of claim 1, wherein the first vertical field effect transistor has a first threshold voltage and the second vertical field effect transistor has a second threshold voltage that is less than the first threshold voltage.

3. The method of claim 1, wherein the first vertical field effect transistor has a first switching speed and the second vertical field effect transistor has a second switching speed that is faster than the first switching speed.

4. The method of claim 1, wherein a thickness of the extra sacrificial layer is approximately equal to a difference in heights of the first upper dielectric spacer and the second upper dielectric spacer, following the isotropic etch process.

5. The method of claim 1, wherein a thickness of the extra sacrificial layer is approximately 2-5 nm and wherein a difference in heights of the first upper dielectric spacer and the second upper dielectric spacer following the isotropic etch process is approximately 2-5 nm.

6. The method of claim 1, further comprising:

before the performing of the multiple etch processes, forming the following;

a first lower source/drain region adjacent to the first multi-layer fin and a second lower source/drain region adjacent to the second multi-layer fin;

a first lower dielectric spacer adjacent to the first multi-layer fin above the first lower source/drain region and a second lower dielectric spacer adjacent to the second multi-layer fin above the second lower source/drain region; and

a first gate adjacent to the first multi-layer fin above the first lower dielectric spacer and a second gate adjacent to the second multi-layer fin above the second lower dielectric spacer, wherein the first gate and the second gate have essentially equal gate lengths and essentially co-planar top surfaces that are below a level of the sacrificial layers; and

,

after the performing of the multiple etch processes, forming a first upper source/drain region fin above the first upper dielectric spacer and a second upper source/drain region above the second upper dielectric spacer.

7. The method of claim 6, wherein the first upper dielectric spacer, the second upper dielectric spacer, the first lower dielectric spacer, and the second lower dielectric spacer comprise silicon nitride spacers.

8. A method comprising:

providing a semiconductor layer;

forming a stack of sacrificial layers on the semiconductor layer, the forming of the stack comprising;

forming a first sacrificial layer on a first device region of the semiconductor layer;

forming a second sacrificial layer on a second device region of the semiconductor layer and on the first sacrificial layer;

forming a third sacrificial layer over the second sacrificial layer; and

forming a fourth sacrificial layer over the third sacrificial layer such that the stack of sacrificial layers has a first portion on the first device region and a second portion on the second device region and such that, within the first portion, the first sacrificial layer is an extra sacrificial layer;

etching a first multi-layer fin in the first portion and the semiconductor layer and a second multi-layer fin in the second portion and the semiconductor layer; and

concurrently forming a first vertical field effect transistor using the first multi-layer fin and a second vertical field effect transistor using the second multi-layer fin, the concurrently forming comprising;

forming a first upper dielectric spacer above a first gate and on first sidewalls of the first multi-layer fin and a second upper dielectric spacer above a second gate and on second sidewalls of the second multi-layer fin; and

performing multiple etch processes that remove the sacrificial layers from the first multi-layer fin and the second multi-layer fin to create a first semiconductor fin and a second semiconductor fin, respectively,

wherein the multiple etch processes comprise;

initial etch processes that remove all of the sacrificial layers except the extra sacrificial layer on the first multi-layer fin; and

an isotropic etch process that removes the extra sacrificial layer from the first multi-layer fin and etches back the first upper dielectric spacer and the second upper dielectric spacer,

wherein, during the isotropic etch process, the first upper dielectric spacer is partially protected by the extra sacrificial layer until the extra sacrificial layer is removed such that the second upper dielectric spacer is etched back faster than the first upper dielectric spacer and such that, following the isotropic etch process, the first upper dielectric spacer is positioned laterally adjacent to the first semiconductor fin, the second upper dielectric spacer is positioned laterally adjacent to the second semiconductor fin, and the first upper dielectric spacer is taller than the second upper dielectric spacer.

9. The method of claim 8, wherein the first sacrificial layer comprises a sacrificial silicon nitride layer, the second sacrificial layer comprises a sacrificial silicon dioxide layer, the third sacrificial layer comprises a sacrificial amorphous silicon layer and the fourth sacrificial layer comprises an additional sacrificial silicon nitride layer.

10. The method of claim 8, wherein the first vertical field effect transistor has a first threshold voltage and the second vertical field effect transistor has a second threshold voltage that is less than the first threshold voltage.

11. The method of claim 8, wherein the first vertical field effect transistor has a first switching speed and the second vertical field effect transistor has a second switching speed that is faster than the first switching speed.

12. The method of claim 8, wherein a thickness of the extra sacrificial layer is approximately equal to a difference in heights of the first upper dielectric spacer and the second upper dielectric spacer, following the isotropic etch process.

13. The method of claim 8, wherein a thickness of the extra sacrificial layer is approximately 2-5 nm and wherein a difference in heights of the first upper dielectric spacer and the second upper dielectric spacer following the isotropic etch process is approximately 2-5 nm.

14. The method of claim 8, further comprising:

before the performing of the multiple etch processes, forming the following;

a first lower source/drain region adjacent to the first multi-layer fin and a second lower source/drain region adjacent to the second multi-layer fin;

a first lower dielectric spacer adjacent to the first multi-layer fin above the first lower source/drain region and a second lower dielectric spacer adjacent to the second multi-layer fin above the second lower source/drain region, wherein the first gate is adjacent to the first multi-layer fin above the first lower dielectric spacer and the second gate is adjacent to the second multi-layer fin above the second lower dielectric spacer, and wherein the first gate and the second gate have essentially equal gate lengths and essentially co-planar top surfaces that are below a level of the sacrificial layers; and

after the performing of the multiple etch processes, forming a first upper source/drain region adjacent the first semiconductor fin above the first upper dielectric spacer and a second upper source/drain region adjacent to the second semiconductor fin above the second upper dielectric spacer.

15. The method of claim 14, wherein the first upper dielectric spacer, the second upper dielectric spacer, the first lower dielectric spacer, and the second lower dielectric spacer comprise silicon nitride spacers.