Bypass techniques to protect noise sensitive circuits within integrated circuit chips
First Claim
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1. An integrated circuit (IC) chip, comprising:
- a circuit coupled between a power supply pad and a first ground pad of the IC chip;
a first bypass path coupled between the power supply pad and a second ground pad of the IC chip, the first bypass path providing a path for noise current around the circuit; and
a second bypass path coupled between the power supply pad and a third ground pad of the IC chip, the second bypass path providing a path for noise current around the circuit;
wherein the second and third ground pads are separate from the first ground pad.
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Abstract
Bypass techniques are provided herein to protect noise sensitive circuits from both internal and external noise sources. According to one embodiment, an integrated circuit (IC) chip may include a noise sensitive circuit coupled between a power supply pad and a first ground pad of the IC chip. In order to protect the first ground pad of the noise sensitive circuit, two distinct bypass paths are provided to route noise current around the noise sensitive circuit. Each bypass path terminates in its own ground pad (e.g., a second ground pad and third ground pad), which is separate from the first ground pad of the noise sensitive circuit.
7 Citations
29 Claims
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1. An integrated circuit (IC) chip, comprising:
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a circuit coupled between a power supply pad and a first ground pad of the IC chip; a first bypass path coupled between the power supply pad and a second ground pad of the IC chip, the first bypass path providing a path for noise current around the circuit; and a second bypass path coupled between the power supply pad and a third ground pad of the IC chip, the second bypass path providing a path for noise current around the circuit; wherein the second and third ground pads are separate from the first ground pad. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An electronic system, comprising:
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a printed circuit board having at least one power conductor and at least one ground conductor; at least one integrated circuit (IC) chip mounted onto the printed circuit board, wherein the at least one IC chip comprises; a power supply pad coupled to the at least one power conductor; a first ground pad, a second ground pad and a third ground pad, each separately coupled to the at least one ground conductor; a circuit coupled between the power supply pad and the first ground pad; a first bypass path coupled between the power supply pad and the second ground pad, the first bypass path providing a path for noise current around the circuit to the second ground pad; and a second bypass path coupled between the power supply pad and the third ground pad, the second bypass path providing a path for noise current around the circuit to the third ground pad. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A method to bypass noise in an integrated circuit (IC) chip, comprising:
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operating an integrated circuit (IC) chip, the IC chip including a circuit coupled between a power supply pad and a first ground pad of the IC chip, a first bypass path coupled between the power supply pad and a second ground pad of the IC chip, and a second bypass path coupled between the power supply pad and a third ground pad of the IC chip; receiving noise current associated with operation of the IC chip; and bypassing the noise current around the circuit using the first bypass path and the second bypass path. - View Dependent Claims (25, 26, 27, 28, 29)
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Specification