Device and method for body-bias

• US 9,964,977 B2
• Filed: 10/30/2015
• Issued: 05/08/2018
• Est. Priority Date: 10/30/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tseng, Chien-Chung, Yuan, Lipen, Shao, Jhih-Jie, Li, Chien-Jung
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US14/929,062
• Publication Number:
  US 20170123444A1
• Time in Patent Office: 921 Days
• CPC Class Codes: G05F 1/59 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H03L 1/00 Stabilisation of generator output against variations of physical values, e.g. power supply
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop

Abstract

A device is disclosed that includes a delay circuit, a detection circuit, and a bias circuit. The delay circuit is configured to generate an oscillating signal in response to a reference signal, a first bias voltage, and a second bias voltage. The detection circuit is configured to compare the oscillating signal with the reference signal, to generate a detect signal. The bias circuit is configured to adjust the first bias voltage and the second bias voltage according to the detect signal and a reference voltage.

Claims

1. A device, comprising:

a delay circuit configured to generate an oscillating signal in response to a reference signal, a first bias voltage, and a second bias voltage;

a detection circuit, comprising a frequency detector configured to compare the oscillating signal with the reference signal, in order to generate a detect signal; and

a bias circuit configured to adjust the first bias voltage and the second bias voltage according to the detect signal and a reference voltage,

wherein the delay circuit comprises a first-type transistor and a second-type transistor that are configured to introduce a delay to the reference signal to generate the oscillating signal, a bulk terminal of the first-type transistor is configured to receive the first bias voltage, and a bulk terminal of the second-type transistor is configured to receive the second bias voltage.

2. The device of claim 1, wherein the delay circuit comprises a plurality of inverters coupled in cascade and the plurality of inverters are configured to introduce the delay to the reference signal, the first-type transistor and the second-type transistor are configured to operate as one of the plurality of inverters, and wherein the first-type transistor is an N-type transistor, and the second-type transistor is a P-type transistor coupled to the N-type transistor in cascade.

3. The device of claim 2, wherein the bias circuit comprises:

a comparator configured to generate a control signal in response to the detect signal and the reference voltage; and

a bias voltage regulator configured to adjust the first bias voltage and the second bias voltage in response to the control signal.

4. The device of claim 3, wherein the bias voltage regulator is further configured to stop adjusting the first bias voltage and the second bias voltage when the adjusted first bias voltage is higher than a conduction voltage of an intrinsic body diode of the N-type transistor, or when the adjusted second bias voltage is lower than a conduction voltage of an intrinsic body diode of the P-type transistor.

5. The device of claim 3, wherein the bias voltage regulator is further configured to stop adjusting the first bias voltage and the second bias voltage when the adjusted first bias voltage is higher than a first predetermined voltage, or when the adjusted second bias voltage is lower than a second predetermined voltage, and

wherein the first predetermined voltage is defined according to a maximum leakage current of the N-type transistor, and the second predetermined voltage is defined according to a maximum leakage current of the P-type transistor.

6. The device of claim 1, wherein the delay is configured to indicate a delay introduced by a critical path of a chip.

7. The device of claim 1, wherein the delay circuit, the detection circuit, and the bias circuit are disposed on a chip or a wafer, the first bias voltage is configured to be applied to a bulk terminal of an N-type transistor in the chip, and the second bias voltage is configured to be applied to a bulk terminal of a P-type transistor in the chip.

8. The device of claim 7, further comprising:

a memory configured to store the first bias voltage and the second bias voltage adjusted by the bias circuit, and generate a control code; and

a power regulator configured to generate a first calibrated bias voltage for the N-type transistor in the chip and a second calibrated bias voltage for the P-type transistor in the chip according to the control code.

9. The device of claim 8, wherein the memory and the power regulator are disposed on the chip, the delay circuit, and the detection circuit, the bias circuit are disposed on a testing line of the wafer, and the chip is disposed on the wafer.

10. The device of claim 1, wherein the frequency detector is configured to compare the oscillating signal with the reference signal to generate an up signal and a down signal, and the detection circuit further comprises:

a charge pump configured to charge or discharge an output terminal of the charge pump according to the up signal and the down signal; and

a loop filter configured to generate the detect signal in response to a voltage level of the output terminal of the charge pump.

11. The device of claim 1, further comprising:

a variation independent voltage reference circuit configured to generate the reference voltage.

12. A device comprising:

a delay circuit comprising at least one inverter, and configured to introduce a delay to a reference signal through the at least one inverter to generate an oscillating signal, and the delay being adjusted according to a first bias voltage and a second bias voltage; and

a bias circuit configured to adjust the first bias voltage and the second bias voltage according to a difference between the reference signal and the oscillating signal,

wherein the at least one inverter comprises a first-type transistor and a second-type transistor, a bulk terminal of the first-type transistor is configured to receive the first bias voltage, and a bulk terminal of the second-type transistor is configured to receive the second bias voltage.

13. The device of claim 12, further comprising:

a frequency detector configured to generate an up signal and a down signal according to the difference between the reference signal and the oscillating signal;

a charge pump configured to charge or discharge an output terminal of the charge pump according to the up signal and the down signal; and

a loop filter configured to generate a detect signal in response to a voltage level of the output terminal of the charge pump.

14. The device of claim 13, wherein the bias circuit comprises:

a comparator configured to generate a control signal in response to the detect signal and a reference voltage; and

a bias voltage regulator configured to adjust the first bias voltage and the second bias voltage in response to the control signal.

15. The device of claim 12, wherein the delay is configured to indicate a delay introduced by a critical path of a chip.

16. A method comprising:

generating an oscillating signal, by a delay circuit, according to a reference signal, a first bias voltage, and a second bias voltage,

wherein a delay is introduced, by a first-type transistor and a second-type transistor in the delay circuit, to the reference signal to generate the oscillating signal, a bulk terminal of the first-type transistor is configured to receive the first bias voltage, and a bulk terminal of the second-type transistor is configured to receive the second bias voltage;

comparing the oscillating signal with the reference signal, by a frequency detector of a detection circuit, to adjust a voltage level of a node of the detection circuit, in order to generate a detect signal in response to the voltage level of the node; and

adjusting the first bias voltage and the second bias voltage, by a bias circuit, according to the detect signal and a reference voltage.

17. The method of claim 16, wherein the first-type transistor is a P-type transistor, the second-type transistor is an N-type transistor, the P-type transistor and the N-type transistor are configured to operate as an inverter for introducing the delay, and the delay is adjusted by the first bias voltage and the second bias voltage and is configured to indicate a delay introduced by a critical path of a chip.

18. The method of claim 16, wherein the comparing the oscillating signal comprises:

comparing the oscillating signal with the reference signal, by the frequency detector of the detection circuit, to generate an up signal and a down signal;

charging or discharging an output terminal of a charge pump of the detection circuit according to the up signal and the down signal, wherein the output terminal of the charge pump corresponds to the node of the detection circuit; and

generating the detect signal, by a loop filter of the detection circuit, in response to a voltage level of the output terminal of the charge pump.

19. The method of claim 16, wherein the adjusting the first bias voltage and the second bias voltage comprises:

generating a control signal, by a comparator of the bias circuit, in response to the detect signal and the reference voltage; and

adjusting the first bias voltage and the second bias voltage, by a bias voltage regulator of the bias circuit, in response to the control signal.

20. The method of claim 19, further comprising:

storing the first bias voltage and the second bias voltage adjusted by the bias voltage regulator to a memory;

generating a control code, by the memory, according to the adjusted first bias voltage and the second bias voltage; and

generating a first calibrated bias voltage and a second calibrated bias voltage, by a power regulator, to bulk terminals of transistors in a chip according to the control code.