Radio frequency power amplifier and method thereof

• US 9,964,985 B1
• Filed: 04/07/2017
• Issued: 05/08/2018
• Est. Priority Date: 04/07/2017
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Leong, Poh-Boon
• Primary Examiner(s): Jager, Ryan
• Application Number:
  US15/481,710
• Time in Patent Office: 396 Days
• Field of Search: 327537
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: H03F 2200/541 Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2203/45481 the CSC comprising only a direct connection to the supply voltage, no other components being present
• CPC Class Codes: H03F 2203/45731 the LC comprising a transformer
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/265 with field-effect transistors only
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence

Abstract

An apparatus having a first coupling network configured to receive an input voltage and output a first gate voltage and a second gate voltage at a first gate node and a second gate node, respectively; a stacked complementary common-source amplifier pair including a first common-source amplifier and a second common-source amplifier configured to receive the first gate voltage and the second gate voltage and output a first drain voltage and a second drain voltage at a first drain node and a second drain node, respectively; a second coupling network configured to provide a coupling between the first drain node and the second drain node to equalize the first drain voltage and the second drain voltage. A first inductor and second inductor couple the first and second drain nodes to a first and second DC node, respectively. Third and fourth inductors are coupled to the first and second inductor.

Claims

1. An apparatus comprising:

a first coupling network configured to receive an input voltage and output a first gate voltage and a second gate voltage at a first gate node and a second gate node, respectively;

a stacked complementary common-source amplifier pair including a first common-source amplifier and a second common-source amplifier configured to receive the first gate voltage and the second gate voltage and output a first drain voltage and a second drain voltage at a first drain node and a second drain node, respectively;

a second coupling network configured to provide a coupling between the first drain node and the second drain node to equalize the first drain voltage and the second drain voltage;

a first inductor configured to couple the first drain node to a first DC node;

a second inductor configured to couple the second drain node to a second DC node;

a third inductor configured to be inductively coupled with the first inductor; and

a fourth inductor configured to be inductively coupled with the second inductor; and

an output combiner configured to output an output voltage in accordance with a combination of a voltage of the third inductor and a voltage of the fourth inductor.

2. The apparatus of claim 1, wherein the first DC node is a ground node and the first common-mode amplifier includes a PMOS (p-channel metal oxide semiconductor) transistor, wherein a gate terminal of the PMOS transistor connects to the first gate node, a drain terminal of the PMOS transistor connects to the first drain node, and a source terminal of the PMOS transistor connects to a common source node.

3. The apparatus of claim 2, wherein the second DC node is a power node and the second common-source amplifier includes a NMOS (n-channel metal oxide semiconductor) transistor, wherein a gate terminal of the NMOS transistor connects to the second gate node, a drain terminal of the NMOS transistor connects to the second drain node, and a source terminal of the NMOS transistor connects to the common source node.

4. The apparatus of claim 1, wherein the first coupling network is configured to provide a coupling between the input voltage and the first gate voltage, and also a coupling between the input voltage and the second gate voltage, so that both the first gate voltage and the second gate voltage effectively track the input voltage at a frequency of interest.

5. The apparatus of claim 4, wherein the first coupling network includes a capacitor configured to provide a AC (alternate current) coupling between the input voltage and one of the first gate voltage and the second gate voltage.

6. The apparatus of claim 4, wherein the first coupling network includes a resistor configured to provide a DC (direct current) coupling between a bias voltage and one of the first gate voltage and the second gate voltage.

7. The apparatus of claim 4, wherein the first coupling network includes an inductor configured to provide a DC (direct current) coupling between a bias voltage and one of the first gate voltage and the second gate voltage.

8. The apparatus of claim 4, wherein the first coupling network includes a transformer configured to provide a AC (direct current) coupling between the input voltage and one of the first gate voltage and the second gate voltage.

9. The apparatus of claim 1, wherein the second coupling network is configured to provide a low impedance at a second harmonic of a frequency of interest.

10. The apparatus of claim 1, wherein the second coupling network includes a capacitor.

11. A method comprising:

receiving an input signal;

coupling the input signal to a first gate signal and a second gate signal at a first gate node and a second gate node, respectively, using a first coupling network;

converting the first gate signal and the second gate signal into a first drain signal and a second drain signal using a first common-source amplifier and a second common-source amplifier, respectively;

shorting a source terminal of the first common-source amplifier to a source terminal of the second common-source amplifier;

coupling the first drain signal and the second drain signal to a first DC (direct current) node and a second DC node via a first inductor and a second inductor, respectively;

coupling the first drain signal to the second drain signal via a second coupling network;

incorporating a third inductor and a fourth inductor configured to inductively couple to the first inductor and the second inductor, respectively; and

combining a voltage of the third inductor and a voltage of the fourth inductor using an output combiner circuit.

12. The method of claim 11, wherein the first DC node is a ground node and the first common-mode amplifier includes a PMOS (p-channel metal oxide semiconductor) transistor, wherein a gate terminal of the PMOS transistor connects to the first gate node, a drain terminal of the PMOS transistor connects to a first drain node, and a source terminal of the PMOS transistor connects to a common source node.

13. The method of claim 12, wherein the second DC node is a power node and the second common-source amplifier includes a NMOS (n-channel metal oxide semiconductor) transistor, wherein a gate terminal of the NMOS transistor connects to a second gate node, a drain terminal of the NMOS transistor connects to the second drain node, and a source terminal of the NMOS transistor connects to the common source node.

14. The method of claim 11, wherein the first coupling network is configured to provide a coupling between the input signal and the first gate signal, and also a coupling between the input signal and the second gate signal, so that both the first gate signal and the second gate signal effectively track the input signal at a frequency of interest.

15. The method of claim 14, wherein the first coupling network includes a capacitor configured to provide a AC (alternate current) coupling between the input signal and one of the first gate signal and the second gate signal.

16. The method of claim 14, wherein the first coupling network includes a resistor configured to provide a DC (direct current) coupling between a bias voltage and one of the first gate signal and the second gate signal.

17. The method of claim 14, wherein the first coupling network includes an inductor configured to provide a DC (direct current) coupling between a bias voltage and one of the first gate signal and the second gate signal.

18. The method of claim 14, wherein the first coupling network includes a transformer configured to provide a AC (direct current) coupling between the input signal and one of the first gate signal and the second gate signal.

19. The method of claim 11, wherein the second coupling network is configured to provide a low impedance at a second harmonic of a frequency of interest.

20. The method of claim 11, wherein the second coupling network includes a capacitor.