Vector operations with operand base system conversion and re-conversion
First Claim
1. A method comprising:
- decoding a single instruction with a hardware decoder of a hardware processor; and
executing the single instruction with a hardware execution unit of the hardware processor by;
receiving a vector element of a first input vector and a vector element of a second input vector expressed in a first base system;
converting the vector element of the first input vector and the vector element of the second input vector into a second lower base system to form a converted vector element of the first input vector and a converted vector element of the second input vector;
performing an operation on the converted vector element of the first input vector and the converted vector element of the second input vector to form a result;
accumulating in a register a portion of the result with a portion of a result of a prior operation expressed in the second lower base system; and
converting contents of the register into the first base system.
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Abstract
Methods and apparatuses relating to vector operations with operand base system conversion and re-conversion are described. In one embodiment, a method includes executing a single instruction by receiving a vector element of a first input vector and a vector element of a second input vector expressed in a first base system, converting the vector elements into a second lower base system to form a converted vector element of the first input vector and a converted vector element of the second input vector, performing an operation on the converted vector element of the first input vector and the converted vector element of the second input vector to form a result, accumulating in a register a portion of the result with a portion of a result of a prior operation expressed in the second lower base system, and converting contents of the register into the first base system.
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Citations
24 Claims
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1. A method comprising:
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decoding a single instruction with a hardware decoder of a hardware processor; and executing the single instruction with a hardware execution unit of the hardware processor by; receiving a vector element of a first input vector and a vector element of a second input vector expressed in a first base system; converting the vector element of the first input vector and the vector element of the second input vector into a second lower base system to form a converted vector element of the first input vector and a converted vector element of the second input vector; performing an operation on the converted vector element of the first input vector and the converted vector element of the second input vector to form a result; accumulating in a register a portion of the result with a portion of a result of a prior operation expressed in the second lower base system; and converting contents of the register into the first base system. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A hardware processor comprising:
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a hardware decoder to decode a single instruction; and a hardware execution unit to execute the single instruction to; receive a vector element of a first input vector and a vector element of a second input vector expressed in a first base system; convert the vector element of the first input vector and the vector element of the second input vector into a second lower base system to form a converted vector element of the first input vector and a converted vector element of the second input vector; perform an operation on the converted vector element of the first input vector and the converted vector element of the second input vector to form a result; accumulate in a register a portion of the result with a portion of a result of a prior operation expressed in the second lower base system; and convert contents of the register into the first base system. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
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decoding a single instruction with a hardware decoder of a hardware processor; and executing the single instruction with a hardware execution unit of the hardware processor by; receiving a vector element of a first input vector and a vector element of a second input vector expressed in a first base system; converting the vector element of the first input vector and the vector element of the second input vector into a second lower base system to form a converted vector element of the first input vector and a converted vector element of the second input vector; performing an operation on the converted vector element of the first input vector and the converted vector element of the second input vector to form a result; accumulating in a register a portion of the result with a portion of a result of a prior operation expressed in the second lower base system; and converting contents of the register into the first base system. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A non-transitory machine readable medium that stores code that when executed by a machine causes the machine to perform a method comprising:
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decoding a single instruction with a hardware decoder of a hardware processor; and executing the single instruction with a hardware execution unit of the hardware processor by; receiving a vector element multiplicand and a vector element multiplier expressed in a first base system; converting the vector element multiplicand and vector element multiplier into a second lower base system to form a converted vector element multiplicand and a converted vector element multiplier; multiplying the converted vector element multiplicand and the converted vector element multiplier to form a multiplication result; accumulating in a register a portion of the multiplication result with a portion of a result of a prior multiplication of operands expressed in the second lower base system; and converting contents of the register into the first base system. - View Dependent Claims (20, 21, 22, 23, 24)
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Specification