Systems and methods of pipelined output latching involving synchronous memory arrays

• US 9,966,118 B2
• Filed: 12/13/2016
• Issued: 05/08/2018
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: GSI Technology Incorporated
• Original Assignee: GSI Technology Incorporated
• Inventors: Shu, Lee-Lean, Sato, Yoshinori
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US15/377,981
• Publication Number:
  US 20170125074A1
• Time in Patent Office: 511 Days
• Field of Search: 3652331, 36518915, 365205
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2207/2272 Latency related aspects
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.

Claims

1. A synchronous memory device, comprising:

memory circuitry having a memory output (Q) and including;

a sense amplifier having a first output and a second output;

a first data path (B1) coupled to the first output of the sense amplifier, the first data path having 2 latches;

a second data path (B2) coupled to the second output of the sense amplifier, the second data path having 3 latches;

wherein the first data path and the second data path are combined by output circuitry to provide a double data rate output; and

wherein the first latch in the first data path receives a clock signal having a trailing edge triggered from a sense amplifier tracking delay signal and the first latch latches data on the first output of the sense amplifier in response to the trailing edge of the clock signal.

2. The device of claim 1, wherein, as a function of the first latch operation, a window for latching includes latching that occurs on a 1st cycle as well as latching that occurs later in time including a duration that extends out beyond the 1st cycle.

3. The device of claim 1, wherein the first latch in the first data path stores the (N−

1) data.

4. The device of claim 1, wherein as a function of arrangement and switching/operating of the first latch in the first data path, a window for latching is extended to include latching on the 1st cycle and out beyond the 1st cycle.

5. The device of claim 1, wherein data from the sense amplifier is available over an availability data window to the data path circuitry.

6. The device of claim 1, wherein as a function of data from the sense amplifier being provided for a longer availability data window via use of the sense amplifier tracking delay signal as input to the first latch, a time period for latching outputs to the double data rate output is extended to include latching on the 1st cycle and out beyond the 1st cycle.

7. The device of claim 1, wherein the first latch in the first data path is operated as a function of the sense amplifier tracking delay signal, independent of cycle time, for all levels of read latency.

8. A synchronous memory device, comprising:

memory circuitry having a memory output (Q) and including;

a sense amplifier having a first output and a second output;

a first data path (B1) coupled to the first output of the sense amplifier, the first data path having 2 latches/registers;

a second data path (B2) coupled to the second output of the sense amplifier, the second data path having 3 latches/registers;

wherein the first data path and the second data path are combined by output circuitry to provide a double data rate output; and

wherein the first latch/register of the first data path receives a clock signal having a trailing edge triggered from a sense amplifier tracking delay signal and the first latch/register latches data on the first output of the sense amplifier in response to the trailing edge of the clock signal.

9. The device of claim 8, wherein the first latch/register of the first data path extends availability of data from the sense amplifier, such that a window for latching previous cycle data (N−

1) is extended to include latching on the 1st cycle (N) and out beyond the 1st cycle (N+1).

10. The device of claim 8, wherein the first latch/register of the first data path is set as a function of whether or not the sense amplifier timing delay information yields an output in the first cycle, or in a later cycle, including:

for (N−

1) sense amplifier output, at cycle N, latch previous cycle (N−

1) data taken from the SA tracking delay, to be available for a later register/latch stage of the pipeline.

11. The device of claim 8 further comprising a sense amplifier pre-charge clock that provides the sense amplifier tracking delay signal.

12. The device of claim 8, wherein, as a function of the first latch/register operation, a window for latching includes latching that occurs on a 1st cycle as well as latching that occurs later in time including a duration that extends out beyond the 1st cycle.

13. The device of claim 8, wherein the first latch/register of the first data path latches the previous cycle data independent of the cycle time.

14. The device of claim 8, wherein the first latch/register of the first data path stores the (N−

1) data.

15. The device of claim 8, wherein the first latch/register of the first data path extends a window for latching to include latching on the 1st cycle and out beyond the 1st cycle.

16. The device of claim 8, wherein data from the sense amplifier is available over an availability data window to the data path circuitry.

17. The device of claim 8, wherein the first latch/register of the first data path extends, as a function of data from the sense amplifier being provided for a longer availability data window via use of the sense amplifier tracking delay signal as input to the first latch/register, a time period for latching outputs to the double data rate output to include latching on the 1st cycle and out beyond the 1st cycle.

18. The device of claim 8, wherein the first latch/register of the first data path is operated as a function of the sense amplifier tracking delay signal, independent of cycle time, for all levels of read latency.

19. The device of claim 8, wherein the first latch/register of the first data path extends availability of data from the sense amplifier, such that a window for latching previous cycle data (N−

1) is extended to include latching on the 1st cycle (N) and out beyond the 1st cycle (N+1).

20. The device of claim 8, wherein the first latch/register of the first data path is set as a function of whether or not the sense amplifier timing delay information yields an output in the first cycle, or in a later cycle, including:

for (N−

1) sense amplifier output, at cycle N, latch previous cycle (N−

1) data taken from the SA tracking delay, to be available for a later register/latch stage of the pipeline.