Method for programming a non-volatile memory device and a method for operating a system having the same

• US 9,966,132 B2
• Filed: 04/04/2017
• Issued: 05/08/2018
• Est. Priority Date: 10/11/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yim, Hye Jin, Park, Il Han, Park, Hyun Kook, Yun, Sung Won
• Primary Examiner(s): Auduong, Gene
• Application Number:
  US15/478,679
• Publication Number:
  US 20180102167A1
• Time in Patent Office: 399 Days
• Field of Search: 36518503, 36518518, 36518519, 36518522, 36518523, 36518524
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Abstract

A method for programming a non-volatile memory device includes programming a lower bit in a memory cell included in the non-volatile memory device, reading the lower bit programmed in the memory cell before programming an upper bit in the memory cell, determining a threshold voltage of the memory cell according to a result of reading the lower bit, determining a type of the memory cell using the threshold voltage, and supplying one of a plurality of pulses to a bit line connected to the memory cell according to the determined type of the memory cell.

Claims

1. A method for programming a non-volatile memory device comprising:

programming a lower bit in a memory cell included in the non-volatile memory device;

reading the lower bit programmed in the memory cell before programming an upper bit in the memory cell;

determining a threshold voltage of the memory cell according to a result of reading the lower bit;

determining a type of the memory cell using the threshold voltage; and

supplying one of a plurality of pulses to a bit line connected to the memory cell according to the determined type of the memory cell.

2. The method for programming a non-volatile memory device of claim 1, wherein reading the lower bit is performed at different time points using different read voltages.

3. The method for programming a non-volatile memory device of claim 1, further comprising programming the upper bit in the memory cell after one of the plurality of pulses is supplied to the bit line.

4. The method for programming a non-volatile memory device of claim 3, wherein the upper bit is programmed in the memory cell according to incremental step pulse programming (ISPP), and

the upper bit is programmed in the memory cell before a programming start voltage, determined according to the ISPP, is supplied to the memory cell.

5. The method for programming a non-volatile memory device of claim 1, wherein heights of the plurality of pulses are different from one another.

6. The method for programming a non-volatile memory device of claim 5, wherein supplying one of the plurality of pulses comprises:

supplying a first pulse among the plurality of pulses to the bit line when the determined type of the memory cell is a first type cell, and

supplying a second pulse among the plurality of pulses is supplied to the bit line when the determined type of the memory cell is a second type cell,

wherein the first pulse has a first height and the second pulse has a second height, and

wherein a first threshold voltage of the first type cell is greater than a second threshold voltage of the second type cell and the first height is higher than the second height.

7. The method for programming a non-volatile memory device of claim 1, wherein the memory cell is a multi-level cell, the upper bit is a most significant bit (MSB), and the lower bit is a least significant bit (LSB).

8. The method for programming a non-volatile memory device of claim 7, wherein the lower bit is programmed as logical 1.

9. The method for programming a non-volatile memory device of claim 1, wherein the memory cell is a three-dimensional memory cell.

10. A method of operating a memory system including a controller and a non-volatile memory device configured to perform a programming operation according to a control of the controller, the method comprising:

programming, by the non-volatile memory device, a lower bit in a memory cell included in the non-volatile memory device;

reading, by the non-volatile memory device, the lower bit programmed in the memory cell before programming an upper bit in the memory cell;

determining, by the non-volatile memory device, a threshold voltage of the memory cell according to a result of reading the lower bit;

determining, by the non-volatile memory device, a type of the memory cell using the threshold voltage; and

supplying, by the non-volatile memory device, one of a plurality of pulses to a bit line connected to the memory cell according to the determined type of the memory cell.

11. The method of operating a memory system of claim 10, further comprising programming, by the non-volatile memory device, the upper bit in the memory cell after one of the plurality of pulses is supplied to the bit line.

12. The method of operating a memory system of claim 11, wherein the upper bit is programmed in the memory cell according to incremental step pulse programming (ISPP), and

the upper bit is programmed, by the non-volatile memory device, in the memory cell before a programming start voltage, determined according to the ISPP, is supplied to the memory cell.

13. The method of operating a memory system of claim 10, wherein heights of the plurality of pulses are different from one another.

14. The method of operating a memory system of claim 13,

wherein supplying one of the plurality of pulses comprises:

supplying, by the non-volatile memory device, a first pulse among the plurality of pulses to the bit line when the determined type of the memory cell is a first type cell, and

supplying, by the non-volatile memory device, a second pulse among the plurality of pulses to the bit line when the determined type of the memory cell is a second type cell,

wherein the first pulse has a first height and the second pulse has a second height, and

wherein a first threshold voltage of the first type cell is greater than a second threshold voltage of the second type cell and the first height is higher than the second height.

15. The method of operating a memory system of claim 10, wherein the memory cell is a multi-level cell, the upper bit is a most significant bit (MSB), and the lower bit is a least significant bit (LSB).

16. A method for programming a non-volatile memory device comprising:

programming a lower bit in a memory cell included in the non-volatile memory device;

reading the lower bit programmed in the memory cell before programming an upper bit in the memory cell;

determining a threshold voltage of the memory cell according to a result of reading the lower bit;

determining whether the memory cell is one of a first type cell, a second type cell, or a third type cell using the threshold voltage;

transmitting a pulse sequence comprising a first pulse, a second pulse, and a third pulse; and

supplying, to a bit line connected to the memory cell, the first pulse if the memory cell is the first type cell, the second pulse if the memory cell is the second type cell, and the third pulse if the memory cell is the third type cell,

wherein a first threshold voltage of the first type cell is higher than a second threshold voltage of the second type cell, and the second threshold voltage of the second type cell is higher than a third threshold voltage of the third type cell.

17. The method of claim 16, further comprising:

programming the upper bit of the memory cell after supplying one of the first pulse, the second pulse, or the third pulse to the bit line connected to the memory cell.

18. The method of claim 16, wherein

a first height of the first pulse is greater than a second height of the second pulse, and

the second height of the second pulse is greater than a third height of the third pulse.

19. The method of claim 18, wherein

the first height of the first pulse is substantially the same as a level of a power voltage, and

the third height of the third pulse is greater than a level of a ground voltage.

20. The method of claim 16, wherein

the memory cell is connected to a string selection transistor of the bit line,

the string selection transistor is turned off when the first pulse is supplied, and

the string selection transistor is turned on when the second pulse or the third pulse is supplied.