Flash memory device

• US 9,966,133 B2
• Filed: 08/31/2017
• Issued: 05/08/2018
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Oh, HakJune, Pyeon, Hong Beom, Kim, Jin-Ki
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US15/692,206
• Publication Number:
  US 20170365333A1
• Time in Patent Office: 250 Days
• Field of Search: 36518511, 36518512, 36518533, 36518517, 36518905, 36518915, 365221, 3652331, 365239
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Claims

1. A flash memory device comprising:

a flash memory array;

a first control port configured to receive a chip select signal from a memory controller;

a first clock port configured to receive a first clock signal from the memory controller;

a second clock port configured to transmit a second clock signal, referenced to the first clock signal, to the memory controller;

at least one common data port configured to receive command data and address data in synchronization with the first clock signal while the chip select signal is at an active low logic state;

core circuitry configured to retrieve a read data from the flash memory array in response to the command data; and

data output circuitry configured to transmit the read data to the memory controller in synchronization with the second clock signal.

2. The flash memory device as claimed in claim 1, further comprising a second control port configured to receive a reset signal from the memory controller.

3. The flash memory device as claimed in claim 1, further comprising a status register configured to indicate that the flash memory device is being utilized while the read data is being retrieved from the flash memory array.

4. The flash memory device as claimed in claim 1, further comprising a phase lock loop (PLL) to synchronize the first clock signal and the second clock signal.

5. The flash memory device as claimed in claim 1, further comprising a delay lock loop (DLL) to synchronize the first clock signal and the second clock signal.

6. The flash memory device as claimed in claim 3 wherein the status register is accessible by the memory controller in synchronization with both rising and falling edges of the second clock signal.

7. The flash memory device as claimed in claim 1 wherein the flash memory device is multi-level-cell (MLC) flash memory device.

8. The flash memory device as claimed in claim 1 wherein the flash memory device is comprised of multi-chip package configuration having two or more stacked chips inside a single package.

9. The flash memory device as claimed in claim 8 wherein the two or more stacked chips are commonly coupled to the chip select signal.

10. The flash memory device as claimed in claim 1 wherein the at least one common data port comprises a single-bit data width.

11. The flash memory device as claimed in claim 1 wherein the at least one common data port comprises a multi-bit data width.

12. The flash memory device as claimed in claim 1, wherein the at least one common data port is configured to receive the command data and the address data in synchronization with both rising and falling edges of the first clock signal.

13. The flash memory device as claimed in claim 1, wherein the data output circuitry is configured to transmit the read data to the memory controller in synchronization with both rising and falling edges of the second clock signal.