Thin film transistor having oxide semiconductor layer

• US 9,966,474 B2
• Filed: 05/18/2017
• Issued: 05/08/2018
• Est. Priority Date: 11/16/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US15/598,815
• Publication Number:
  US 20170323975A1
• Time in Patent Office: 355 Days
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Oxide layers which contain at least one metal element that is the same as that contained in an oxide semiconductor layer including a channel are formed in contact with the top surface and the bottom surface of the oxide semiconductor layer, whereby an interface state is not likely to be generated at each of an upper interface and a lower interface of the oxide semiconductor layer. Further, it is preferable that an oxide layer, which is formed using a material and a method similar to those of the oxide layers be formed over the oxide layers Accordingly, the interface state hardly influences the movement of electrons.

Claims

1. A semiconductor device comprising:

a first oxide layer over and in contact with an insulating surface;

an oxide semiconductor layer over and in contact with the first oxide layer;

a second oxide layer over and in contact with the oxide semiconductor layer;

a third oxide layer over and in contact with the second oxide layer;

a gate insulating layer over and in contact with the third oxide layer; and

a gate electrode over and in contact with the gate insulating layer,

wherein each of the first oxide layer, the oxide semiconductor layer, the second oxide layer and the third oxide layer contains indium, gallium and zinc,

wherein the first oxide layer has an atomic ratio of gallium larger than an atomic ratio of indium, and

wherein the third oxide layer has an atomic ratio of gallium larger than an atomic ratio of indium.

2. The semiconductor device according to claim 1, wherein the first oxide layer has an atomic ratio of gallium larger than an atomic ratio of zinc, and the third oxide layer has an atomic ratio of gallium larger than an atomic ratio of zinc.

3. The semiconductor device according to claim 1, wherein the second oxide layer has an atomic ratio of gallium larger than an atomic ratio of indium.

4. The semiconductor device according to claim 1, further comprising a source electrode and a drain electrode interposed between a portion of the second oxide layer and a portion of the third oxide layer.

5. A semiconductor device comprising:

a first oxide layer over and in contact with an insulating surface;

an oxide semiconductor layer over and in contact with the first oxide layer;

a second oxide layer over and in contact with the oxide semiconductor layer;

a third oxide layer over and in contact with the second oxide layer;

a gate insulating layer over and in contact with the third oxide layer; and

a gate electrode over and in contact with the gate insulating layer,

wherein each of the first oxide layer, the oxide semiconductor layer, the second oxide layer and the third oxide layer contains indium, gallium and zinc,

wherein the first oxide layer has an atomic ratio of zinc larger than an atomic ratio of indium, and

wherein the third oxide layer has an atomic ratio of zinc larger than an atomic ratio of indium.

6. The semiconductor device according to claim 5, wherein the first oxide layer has an atomic ratio of gallium larger than an atomic ratio of zinc, and the third oxide layer has an atomic ratio of gallium larger than an atomic ratio of zinc.

7. The semiconductor device according to claim 5, wherein the second oxide layer has an atomic ratio of gallium larger than an atomic ratio of indium.

8. The semiconductor device according to claim 5, further comprising a source electrode and a drain electrode interposed between a portion of the second oxide layer and a portion of the third oxide layer.

9. A semiconductor device comprising:

a first oxide layer over and in contact with an insulating surface;

an oxide semiconductor layer over and in contact with the first oxide layer;

a second oxide layer over and in contact with the oxide semiconductor layer;

a third oxide layer over and in contact with the second oxide layer;

a gate insulating layer over and in contact with the third oxide layer; and

a gate electrode over and in contact with the gate insulating layer,

wherein each of the first oxide layer, the oxide semiconductor layer, the second oxide layer and the third oxide layer contains indium, gallium and zinc,

wherein the first oxide layer has an atomic ratio of gallium larger than an atomic ratio of indium,

wherein the first oxide layer has an atomic ratio of zinc larger than an atomic ratio of indium,

wherein the third oxide layer has an atomic ratio of gallium larger than an atomic ratio of indium, and

wherein the third oxide layer has an atomic ratio of zinc larger than an atomic ratio of indium.

10. The semiconductor device according to claim 9, wherein the first oxide layer has an atomic ratio of gallium larger than an atomic ratio of zinc, and the third oxide layer has an atomic ratio of gallium larger than an atomic ratio of zinc.

11. The semiconductor device according to claim 9, wherein the second oxide layer has an atomic ratio of gallium larger than an atomic ratio of indium.

12. The semiconductor device according to claim 9, further comprising a source electrode and a drain electrode interposed between a portion of the second oxide layer and a portion of the third oxide layer.