Power converter with circuits for providing gate driving

• US 9,966,837 B1
• Filed: 07/07/2017
• Issued: 05/08/2018
• Est. Priority Date: 07/08/2016
• Status: Active Grant

• Current Assignee: VPT, Inc. (Heico Corporation)
• Original Assignee: VPT, Inc. (Heico Corporation)
• Inventors: Seaton, Kevin L.
• Primary Examiner(s): Rosario Benitez, Gustavo
• Application Number:
  US15/644,257
• Time in Patent Office: 305 Days
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/155 using semiconductor devices only
• CPC Class Codes: H02M 3/33546 with automatic control of the output voltage or current H02M3/33561 takes precedence
• CPC Class Codes: H03K 17/691 using transformer coupling

Abstract

A switched mode power supply is provided comprising a pulse-width-modulator (PWM), a power section, and a drive section for the power switch. The drive section consists of a new method of driving the power switch where it is desired that the switch terminals be isolated from the PWM ground. The new driver design, which incorporates a small isolation transformer along with unique modifications to the traditional DC restore circuit, is directed to solving problems when PWM type switching power supplies encounter fault conditions such as a short circuit across their output as well as protecting the switch and the load when an ordinary shutdown or disable command is received. One problem that arises with switch drivers that utilize isolation transformers during an overload event or even an ordinary shutdown event is that the driver does not turn off and hold off the power switch when it is commanded to do so. This invention solves these problems by insuring that the appropriate components are de-energized in the classical dc-restore circuit which will prevent the PWM from losing control of the power switch.

Claims

1. A switched mode power supply (SMPS) comprising:

a pulse-width-modulator (PWM) with a PWM ground referenced positive output, a power section with a power switch (Q1) having a switch control that turns on said switch with a positive voltage at a positive input terminal (GATE) with respect to a negative input terminal (SOURCE) above a threshold voltage and turns off said switch (Q1) with a voltage below said threshold voltage, and a drive section that provides an interface between said PWM and said switch;

wherein said drive section has an input, an output, and an isolation transformer (TX1) disposed in between that isolates the drive section output from the input and having a primary winding (V_P1), a first secondary winding (V_S1a), and a second secondary winding (V_S1b) wherein voltage from said second secondary winding (V_S1b) is opposite in polarity to that of said first secondary winding (V_S1a) output;

wherein said PWM output is connected to said primary winding (V_P1) through a DC-blocking capacitor (C1);

wherein said first secondary winding (V_S1a) high side is connected to the positive input terminal (GATE) of said power switch (Q1) via a DC-restore capacitor (C2), said first secondary winding (V_S1a) low side is connected to the negative input terminal (SOURCE) of said switch (Q1) and, optionally, a DC-restore diode (D2) is added with its cathode connected to said DC-restore capacitor (C2) terminal opposite the capacitor'"'"'s connection to said first secondary winding (V_S1a) high side and with its anode connected to said first secondary winding (V_S1a) low side; and

wherein said second secondary winding (V_S1b) high side is connected to a first control terminal of a DC-restore capacitor (C2) switch module (X3) and said second secondary winding (V_S1b) low side is connected to a second control terminal of said switch module (X3) and to said first secondary winding (V_S1a) low side, wherein said switch module (X3) has a switch connected across said DC-restore capacitor (C2), from the capacitor terminal opposite said first secondary winding (V_S1a) high side to said first secondary winding (V_S1a) low side, wherein said switch module (X3) has timing circuitry which turns off said DC-restore capacitor switch module (X3) after a preset time;

wherein after a voltage pulse is received from said second secondary winding (V_S1b), said DC-restore capacitor switch module (X3) connects said DC-restore capacitor (C2) to said first secondary winding (V_S1a) low side, but only until the preset time has elapsed.

2. The SMPS of claim 1 further including a diode (D1) connected in parallel with said DC-blocking capacitor (C1) with its cathode oriented toward said positive output of said PWM.

3. The SMPS of claim 1 wherein said DC-restore capacitor switch module (X3) comprises an NPN transistor (Q2) and said timing circuitry comprises a timing capacitor (C3) connected to said second secondary winding (V_S1b) high side and to a timing resistor (R3) connected to said transistor (Q2) base whose collector is connected to said DC-restore capacitor (C2) opposite the capacitor'"'"'s connection to said first secondary winding (V_S1a) high side and whose emitter is connected to both of said secondary winding (V_S1a, V_S1b) low sides, further having the cathode of a diode (D3) connected to the junction of said time constant capacitor (C3) and said timing resistor (R3) and having its anode connected to the emitter of said NPN transistor (Q2).

4. The SMPS of claim 3 further including a diode (D1) connected in parallel with said DC-blocking capacitor (C1) with its cathode oriented toward said positive output of said PWM.

5. The SMPS of claim 3 further including Md DC-restore diode (D2) with its anode connected to said first secondary winding (V_S1a) low side and its cathode connected to said DC-restore capacitor (C2) opposite the capacitor'"'"'s connection to said first secondary winding (V_S1a) high side.

6. The SMPS of claim 1 wherein said DC-restore switch module (X3) comprises an N-channel MOSFET (Q2) and said timing circuitry comprises a timing capacitor (C3) connected to said second secondary winding (V_S1b) high side and to the gate of said MOSFET (Q2) and a timing resistor (R3) connected between the gate of said MOSFET (Q2) and said second secondary winding (V_S1b) low side which is connected to the source of said MOSFET (Q2) whose drain is connected to said DC-restore capacitor (C2) opposite the capacitor'"'"'s connection to said first secondary winding (V_S1a) high side.

7. The SMPS of claim 6 further including a diode (D1) connected in parallel with said DC-blocking capacitor (C1) with its cathode oriented toward the positive output of said PWM.

8. The SMPS of claim 6 further including said DC-restore diode (D2) with its anode connected to said first secondary winding (V_S1a) low side and its cathode connected to said DC-restore capacitor (C2) opposite the capacitor'"'"'s connection to said first secondary winding (V_S1a) high side.

9. The SMPS of claim 6 wherein the cathode of a diode (D3) is connected to the junction of said timing capacitor (C3) and said timing resistor (R3) and whose anode is connected to said second secondary winding (S1b) low side.

10. The SMPS of claim 1, further including a diode (DI) connected across said DC-blocking capacitor (C1) with its cathode oriented toward said positive output of said PWM;

further including a DC-restore diode (D2) with its anode connected to said first secondary winding (V_S1a) low side and its cathode connected to said DC-restore capacitor (C2) opposite the capacitor'"'"'s connection to said first secondary winding (V_S1a) high side; and

a DC-restore capacitor shorting switch (SW2) connected across said DC-restore capacitor (C2) having control terminals that turn said switch on after receiving a signal that said PWM has shut down.

11. The SMPS of claim 10 wherein said DC-restore capacitor shorting switch (SW2) comprises a transistor (Q6), which is a PNP transistor having its collector connected to said DC-restore capacitor (C2) at its connection to said first secondary winding (V_S1a) high side, its emitter connected to said DC-restore capacitor (C2) at its connection to the cathode of said DC-restore diode (D2), and its base connected through a resistor (R17) to a disable switch (Q4) that connects said resistor (R17) to said PWM ground immediately after or concurrently when said PWM shuts down.

12. The SMPS of claim 10 wherein said second DC-restore switch comprises a transistor (Q6), which is a P-channel MOSFET transistor having its drain connected to said DC-restore capacitor (C2) at its connection to said first secondary winding (V_S1a) high side, its source connected to said DC-restore capacitor (C2) at its connection to the cathode of said DC-restore diode (D2), and its gate connected through a resistor (R17) to a disable switch (Q4) that connects said resistor (R17) to said PWM ground immediately after or concurrently when said PWM shuts down.

13. A switched mode power supply (SMPS) comprising:

a pulse-width-modulator (PWM) with a PWM ground referenced positive output, a power section with a power switch (Q1) having a switch control that turns on said switch with a positive voltage at a positive input terminal (GATE) with respect to a negative input terminal (SOURCE) above a threshold voltage and turns said switch (Q1) off with a voltage below said threshold voltage, and a drive section that provides an interface between said PWM and said switch;

wherein said drive section has an input, an output, and an isolation transformer (TX1) disposed in between that isolates the drive section output from the input and having a primary winding (V_P1) and at least one secondary winding (V_S1a);

wherein said PWM output is connected to said primary winding (V_P1) through a DC-blocking capacitor (C1);

a diode (D1) connected across said DC-blocking capacitor (C1) with its cathode oriented toward said PWM positive output;

wherein said at least one secondary winding (V_S1a) high side is connected to the positive input terminal (GATE) of said power switch (Q1) via a DC-restore capacitor (C2), said at least one secondary winding (V_S1a) low side is connected to the negative input terminal (SOURCE) of said switch (Q1) as well as to the anode of a DC-restore diode (D2) with its cathode connected to said DC-restore capacitor (C2) terminal opposite the capacitor'"'"'s connection to said first secondary winding (V_S1a) high side and with its anode connected to said first secondary winding (V_S1a) low side; and

a DC-restore capacitor shorting switch (SW2) connected across said DC-restore capacitor (C2) having control terminals that turn said switch on after receiving a signal that turns off said PWM output.

14. The SMPS of claim 13 wherein said DC-restore capacitor shorting switch (SW2) comprises a transistor (Q6), which is a PNP transistor having its collector connected to said DC-restore capacitor (C2) at its connection to said first secondary winding (V_S1a) high side, its emitter connected said DC-restore capacitor (C2) at its connection to the cathode of said DC-restore diode (D2), and its base connected through a resistor (R17) to a disable switch (Q4) that connects said resistor to said PWM ground immediately after or concurrently when said PWM shuts down.

15. The SMPS of claim 13 wherein said second DC-restore switch comprises a P-channel MOSFET transistor (Q6) having its drain connected to said DC-restore capacitor (C2) at its connection to said first secondary winding (V_S1a) high side, its source connected said DC-restore capacitor (C2) at its connection to the cathode of said DC-restore diode (D2), and its gate connected through a resistor (R17) to a disable switch (Q4) that connects said resistor to said PWM ground immediately after or concurrently when said PWM shuts down.

16. A switched mode power supply (SMPS) comprising:

a pulse-width-modulator (PWM) with a PWM ground referenced positive output, a power section with a power switch (Q1) having a switch control that turns on said switch with a positive voltage at a positive input terminal (GATE) with respect to a negative input terminal (SOURCE) above a threshold voltage and turns said switch (Q1) off with a voltage below said threshold voltage, and a drive section that provides an interface between said PWM and said switch;

wherein said drive section has an input, an output, and an isolation transformer (TX0) disposed in between that isolates the drive section output from the input and having a primary winding (V_P0) and a secondary winding (V_S0);

wherein said PWM output is connected to said primary winding (V_P0) through a DC-blocking capacitor (C1);

wherein said secondary winding (V_S0) high side is connected to the positive input terminal (GATE) of said power switch (Q1) via a DC-restore capacitor (C2), said secondary winding (V_S0) low side is connected to the negative input terminal (SOURCE) of said switch (Q1) and, optionally, a DC-restore diode (D2) is added with its cathode connected to said DC-restore capacitor (C2) terminal opposite the capacitor'"'"'s connection to said first secondary winding (V_S0) high side and with its anode connected to said first secondary winding (V_S0) low side; and

wherein said secondary winding (V_S0) is further connected to the control terminals of a DC-restore capacitor (C2) switch module (X4), wherein said switch module (X4) has a switch connected across said DC-restore capacitor (C2), from the capacitor terminal opposite said secondary winding (V_S0) high side to said secondary winding (V_S0) low side, wherein said switch module (X4) has timing circuitry which turns off said DC-restore capacitor switch module (X4) after a preset time;

wherein after a voltage pulse is received from said second secondary winding (V_S0), said DC-restore switch module connects said DC-restore capacitor (C2) to said secondary winding (V_S0) low side, which nuts said DC-restore capacitor (C2) in parallel with said DC-blocking capacitor (C1) to keep V_C2 proportional to V_C1 as scaled by the transformer (TX0) turns ratio, but only until the preset time has elapsed.

17. The SMPS of claim 16 wherein said DC-restore capacitor switch module (X4) comprises a diode-pumped DC supply (C14, D8, D9, C15) that powers a level translator (Q7) turned on and off by timing circuitry (C3, R3, D3) both fed by pulses from said secondary winding (V_S0), controlling in turn a DC-restore capacitor switch (Q2).

18. The SMPS of claim 16 wherein said DC-restore capacitor switch module (X4) comprises:

a coupling capacitor (C14) connected to said secondary winding (V_S0) high side and the cathode of a diode (DS) connected to said secondary winding (V_S0) low side, the junction of the two being connected to the anode of a rectifying diode (D9) which is connected to a DC-supply capacitor (C15), which is also connected to said secondary winding (V_S0) low side, the cathode of said rectifying diode further connected to the cathode of a voltage limiting diode (D3) and the emitter of a PNP transistor;

a timing capacitor (C3) connected to the anode of said rectifying diode (D9) and the anode of said voltage limiting diode (D3) and a timing resistor (R3) connected to the base of said PNP transistor; and

a current limiting resistor (R19) connected to the collector of said PNP transistor, the other side connected to the base of an NPN transistor (Q2) and a turn-off resistor (R20) which is connected to said secondary winding (V_S0) low side and the emitter of said NPN transistor whose collector is connected to said DC-restore capacitor (C2) opposite the capacitor'"'"'s connection to the secondary winding (V_S0) high side.

19. The SMPS of claim 16 further including a diode (DI) connected in parallel with said DC-blocking capacitor (C1) with its cathode oriented toward the positive output of said PWM.

20. The SMPS of claim 19 further including a DC-restore diode (D2) whose anode is connected to a junction of said secondary winding (V_S0) low side and the negative input terminal (SOURCE) of said switch (Q1) with its cathode connected to said DC-restore capacitor (C2) opposite the capacitor'"'"'s connection to the high side of said secondary winding (V_S0).

21. A switched mode power supply (SMPS) comprising:

a pulse-width-modulator (PWM) with a PWM ground referenced positive output, a power section with a power switch (Q1) having a switch control that turns on said switch with a positive voltage at a positive input terminal (GATE) with respect to a negative input terminal (SOURCE) above a threshold voltage and turns said switch (Q1) off with a voltage below said threshold voltage, and a drive section that provides an interface between said PWM and said switch;

wherein said drive section has an input, an output, and an isolation transformer (TX0, TX1) disposed in between that isolates the drive section output from the input and having a primary winding (V_P0, V_P1) and one or more secondary windings (V_S0, V_S1a, V_S1b);

wherein said PWM output is connected to said primary winding (V_P0, V_P1) through a DC-blocking capacitor (C1);

wherein one secondary winding (V_S0, V_S1a) high side is connected as a gate driver to the positive input terminal (GATE) of said power switch (Q1) via a DC-restore capacitor (C2), said secondary winding gate driver (V_S0, V_S1a) low side is connected to the negative input terminal (SOURCE) of said switch (Q1), and, optionally, a DC-restore diode (D2) is added with its cathode connected to said DC-restore capacitor (C2) terminal opposite the capacitor'"'"'s connection to said first secondary winding (V_S1a) high side and with its anode connected to said first secondary winding (V_S0, V_S1a) low side; and

a DC-restore capacitor (C2) switch module (X3, X4) having a switch connected across said DC-restore capacitor (C2), from the capacitor terminal opposite said secondary winding gate driver (V_S0, V_S1a) high side to said secondary winding gate driver (V_S0, V_S1a) low side, wherein said switch module (X3, X4) is configured to accept inputs from one of said one or more secondary windings (V_S0, V_S1a, V_S1b) as a control winding to trigger timing circuitry that controls said DC-restore capacitor switch module (X3, X4) switch;

wherein after a voltage pulse is received from said control winding (V_S0, V_S1a, V_S1b), said DC-restore switch module connects said DC-restore capacitor (C2) to said secondary winding gate driver (V_S0, V_S1a) low side, which puts said DC-restore capacitor (C2) in parallel with said DC-blocking capacitor C1) to keep V_C2 proportional to V_C1 as scaled by the transformer (TX0, TX1) turns ratio, but only until a preset time has elapsed.

22. The SMPS of claim 21 wherein said gate driver and said DC-restore capacitor (C2) switch module (X4) utilize the same winding.

23. The SMPS of claim 21 further including a diode (D1) connected in parallel with said DC-blocking capacitor (C1) with its cathode oriented toward the positive output of said PWM.

24. The SMPS of claim 21 further including said DC-restore diode (D2) with its anode connected to said secondary winding gate driver (V_S0, V_S1a) low side and its cathode connected to said DC-restore capacitor (C2) opposite the capacitor'"'"'s connection to said secondary winding gate driver (V_S0, V_S1a) high side.