Configurable logic circuit including dynamic lookup table

• US 9,966,960 B2
• Filed: 12/17/2014
• Issued: 05/08/2018
• Est. Priority Date: 12/17/2014
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Westwick, Alan Lee, Hong, Soh Kok, Lih, Low Yung
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US14/574,112
• Publication Number:
  US 20160182054A1
• Time in Patent Office: 1,238 Days
• Field of Search: None
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

In some embodiments, a circuit may include a configurable logic module including a multiplexer. The multiplexer may include a plurality of data inputs configured to receive one or more bit strings. Each of the one or more bit strings may correspond to a logic operation. The multiplexer may further include a first control input configured to receive a first input signal, a second control input configured to receive a second input signal, and an output configured to provide an output signal corresponding to a selected logic operation based on the first input signal and the second input signal.

Claims

1. A circuit comprising:

a configurable logic module including;

a multiplexer including;

a plurality of data inputs configured to receive one or more bit strings, each of the one or more bit strings including a plurality of bits corresponding to a logic operation;

a first control input configured to receive a first input signal;

a second control input configured to receive a second input signal, and

an output configured to provide an output signal corresponding to a result of a selected logic operation determined from the plurality of data inputs, the selected logic operation performed on the first input signal and the second input signal to produce an output; and

a register configured to store the one or more bit strings, each of the one or more bit strings including multiple bits, the register including a plurality of outputs coupled to the plurality of data inputs.

2. The circuit of claim 1, wherein:

the multiplexer further includes a third control input configured to receive a third input signal; and

the output signal corresponds to the selected logic operation based on the first input signal, the second input signal, and the third input signal.

3. The circuit of claim 2, wherein:

the plurality of data inputs includes eight data inputs; and

the multiplexer is configurable to implement two hundred fifty-six different logic operations.

4. The circuit of claim 1, further comprising a plurality of input multiplexers, each of the plurality of input multiplexers including a plurality of inputs, at least one control input, and an output coupled to one of the first control input and the second control input of the multiplexer.

5. The circuit of claim 1, further comprising a plurality of configurable logic modules including a second configurable logic module coupled to an output of the first configurable logic module.

6. The circuit of claim 5, wherein:

the second configurable logic module includes an output; and

the configurable logic module and the second configurable logic module cooperate to provide a pulse at the output of the second configurable logic module representing a rising edge of an input signal at the at least one selected input.

7. The circuit of claim 1, further comprising:

a plurality of peripheral circuits, at least one of the plurality of peripheral circuits coupled to a respective one of the plurality of inputs of the configurable logic module; and

a crossbar coupled to an output of the configurable logic module and coupled to the plurality of peripheral circuits and to at least one port driver circuit.

8. A circuit comprising:

a first lookup table macrocell including;

a register including a plurality of outputs, the register configured to store one or more bit strings, each of the one or more bit strings including a plurality of bits configured to represent a logic function of a plurality of logic functions; and

a multiplexer including a plurality of inputs coupled to the plurality of outputs of the register, a plurality of control inputs configured to receive input signals, a carry in input coupled to a carry out output of a second lookup table macrocell, and an output, the multiplexer configured to implement a logic function in response to the input signals and to provide an output signal to the output based on the logic function as applied to the input signals received at the plurality of control inputs and based on a carry out signal at the carry in input.

9. The circuit of claim 8, further comprising an interrupt generator circuit coupled to the output of the multiplexer and configured to generate an interrupt signal in response to the output signal.

10. The circuit of claim 8, wherein the register is programmable.

11. The circuit of claim 10, wherein:

each of the one or more bit strings includes eight bits;

the plurality of inputs includes eight inputs;

the plurality of control inputs includes three control inputs; and

the multiplexer is configurable to provide two hundred fifty-six different logic operations.

12. The circuit of claim 8, further comprising logic circuitry coupled to the output of the multiplexer.

13. The circuit of claim 12, wherein the logic circuitry comprises a synchronous register including an input coupled to the output of the multiplexer, a clock input to receive a clock signal, and a synchronous output to provide the output signal synchronized to the clock signal.

14. The circuit of claim 8, wherein the lookup table macrocell further comprises a carry out output coupled to the output and configured to provide a carry out signal.

15. The circuit of claim 14, further comprising the second lookup table macrocell including:

a first input coupled to the output of the first lookup table macrocell; and

the carry in input coupled to the carry out output of the lookup table macrocell.

16. A method comprising:

providing one or more bit strings to a plurality of data inputs of a first multiplexer, each of the one or more bit strings including a plurality of bits representing a logic operation;

providing one or more second bit strings to a second plurality of inputs of a second multiplexer, each of the one or more second bit strings including a second plurality of bits representing the logic operation;

applying one or more control input signals to one or more control inputs of the first multiplexer and one or more second control input signals to one or more control inputs of the second multiplexer to produce a first multiplexer output and a second multiplexer output, respectively;

providing the first multiplexer output to a first data input of a third multiplexer and the second multiplexer output to a second data input of the third multiplexer;

applying one or more control signals to one or more control inputs of the third multiplexer to determine a selected logic operation; and

providing an output signal to an output of the multiplexer according to the selected logic operation applied to the one or more control input signals.

17. The method of claim 16, wherein providing the one or more bit strings comprises programming a register with the plurality of bit strings, the register including a plurality of outputs coupled to the plurality of data inputs of the multiplexer.

18. The method of claim 17, wherein the register is programmed by a control circuit to provide one or more selected logic operations.

19. The method of claim 16, wherein applying the one or more control input signals to the one or more control inputs comprises multiplexing a plurality of inputs to provide one of the plurality of inputs to a corresponding one of the one or more control inputs of the multiplexer.