Optoelectronic switch

• US 9,967,208 B2
• Filed: 09/05/2017
• Issued: 05/08/2018
• Est. Priority Date: 09/30/2014
• Status: Active Grant

• Current Assignee: Rockley Photonics Limited
• Original Assignee: Rockley Photonics Limited
• Inventors: Rickman, Andrew, Farrington, Nathan
• Primary Examiner(s): Rahll, Jerry
• Application Number:
  US15/696,145
• Publication Number:
  US 20180063029A1
• Time in Patent Office: 245 Days
• Field of Search: None
• CPC Class Codes: G02B 6/356 in an optical cross-connect device, e.g. routing and switching aspects of interconnecting different paths propagating different wavelengths to (re)configure the various input and output links switching polarized beams G02B6/3594; power equalizers G02B6/356 and G02B6/3594; path selecting means H04Q11/0001
• CPC Class Codes: H04J 14/0212 using optical switches or wavelength selective switches [WSS]
• CPC Class Codes: H04J 14/0256 at the optical channel layer
• CPC Class Codes: H04L 49/10 characterised by the switching fabric construction
• CPC Class Codes: H04L 49/111 Switch interfaces, e.g. port details
• CPC Class Codes: H04L 49/112 Switch control, e.g. arbitration
• CPC Class Codes: H04Q 11/0005 Switch and router aspects
• CPC Class Codes: H04Q 11/0071 Provisions for the electrical-optical layer interface
• CPC Class Codes: H04Q 2011/0032 using static wavelength routers (e.g. arrayed waveguide grating router [AWGR] )
• CPC Class Codes: H04Q 2011/006 Full mesh

Abstract

An optoelectronic switch comprising: a first plurality of detector remodulators (DRMs) (C3, D1), each DRM having an integer number M of optical inputs and an integer number N of optical outputs; a second plurality of DRMs (C7, D5), each DRM having N optical inputs and M optical outputs; a passive optical switch fabric (C4+C5+C6, D2+D3+D4) connecting the N optical outputs of each of the first plurality of DRMs with the N optical inputs of each of the second plurality of DRMs, the path of an optical signal through the optical switch fabric depending upon its wavelength; wherein each DRM (C3, D1) of the first plurality of DRMs is configured to act as a tunable wavelength converter to select the desired path of an optical signal through the optical switch fabric (C4+C5+C6, D2+D3+D4); and wherein each of the first plurality of DRMs (C3, D1) includes a concentrator, the concentrator configured to aggregate optical signals received from any of the M inputs of that DRM and to buffer them according to the one of the plurality of second DRMs (C7, D5) that includes their destination port.

Claims

1. A detector remodulator for use in controlling a path through an optoelectronic switch, the detector remodulator comprising:

one or more detectors configured to convert an optical input signal into an electrical output signal;

one or more modulators each having an electrical input and being configured to receive an unmodulated laser input and to generate a modulated optical signal having the wavelength of the laser input and containing information from the electrical output signal from a respective detector; and

an ASIC electrically connecting the electrical output of the detectors to the electrical input of the modulators, the ASIC configured;

to control the concentration of signals destined for a group of outputs of the optoelectronic switch; and

to control the path of the optical signal through the optoelectronic switch.

2. The detector remodulator of claim 1, wherein said one or more detectors is a plurality of detectors and said one or more modulators is a plurality of modulators.

3. The detector remodulator of claim 2, comprising a control interface through which the ASIC is configured to communicate with a single controller to control the path taken by all optical input signals received by all of said detectors through the optoelectronic switch.

4. The detector remodulator of claim 2, comprising a plurality of packet processors;

each packet processor being located downstream from a respective one of the plurality of detectors.

5. The detector remodulator of claim 4, wherein the ASIC includes a virtual output queue configured to store packets from the plurality of packet processors according their destination;

each possible destination corresponding to a group of outputs of an alternative detector remodulator;

wherein the virtual output queue is configured to receive data from the outputs of all of the plurality of packet processors.

6. The detector remodulator of claim 1, wherein the ASIC includes one or more of the following:

a receiver circuit, a transimpedance circuit, and a modulator driver.

7. The detector remodulator of claim 1, wherein the ASIC includes signal regeneration circuitry.

8. The detector remodulator of claim 7, wherein the signal regeneration circuitry includes signal retiming and/or signal reshaping.