Selective designation of multiple cores as bootstrap processor in a multi-core microprocessor

• US 9,971,605 B2
• Filed: 05/19/2014
• Issued: 05/15/2018
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Gaskins, Stephan
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Stewart, Kevin
• Application Number:
  US14/281,709
• Publication Number:
  US 20150067318A1
• Time in Patent Office: 1,457 Days
• Field of Search: 438 14
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate multiple of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate a single processing core of the plurality of processing cores to be the bootstrap processor.

Claims

1. A microprocessor, comprising:

a plurality of processing cores configured to operate in first and second modes;

in the first mode, each of the plurality of processing cores concurrently operates as a bootstrap processor and concurrently executes a respective instance of a test program; and

in the second mode, only a single processing core of the plurality of processing cores operates as the bootstrap processor.

2. The microprocessor of claim 1, further comprising:

a plurality of interrupt controllers corresponding to the plurality of processing cores, wherein each interrupt controller includes an identifier used to determine whether an interrupt request is destined for the corresponding processing core;

in the first mode, each of the plurality of processing cores sets the identifier in the corresponding interrupt controller to a value associated with the bootstrap processor.

3. The microprocessor of claim 1, wherein the microprocessor is further configured to modify upper address bits of memory accesses by each processing core of the plurality of processing cores so that each processing core accesses a unique address space.

4. The microprocessor of claim 1, wherein a holding register designates the first or second mode of operation for the plurality of processing cores.

5. The microprocessor of claim 4, wherein the holding register is configured to receive a sensed evaluation of a fuse that is either blown or unblown.

6. The microprocessor of claim 4, wherein the holding register is configured to receive a value designating the mode from a boundary scan input.

7. The microprocessor of claim 1, wherein each processing core of the plurality of processing cores is configured to determine the mode in response to a reset of the processing core.

8. The microprocessor of claim 1, in the first mode, the plurality of processing cores are configured to set a flag in a respective register of each processing core of the plurality of processing cores to indicate the processing core is the bootstrap processor.

9. A method for configuring a multi-core microprocessor, the method comprising:

determining a mode of the microprocessor;

when the mode is a first mode;

operating, by each of the plurality of processing cores, as a bootstrap processor and concurrently executing, by each of the plurality of processing cores, a respective instance of a test program; and

when the mode is a second mode;

operating, by only a single processing core of the plurality of processing cores, as the bootstrap processor.

10. The method of claim 9,

wherein the microprocessor further includes a plurality of interrupt controllers corresponding to the plurality of processing cores, wherein each interrupt controller includes an identifier used to determine whether an interrupt request is destined for the corresponding processing core;

in the first mode, setting, by each of the plurality of processing cores of the multi-core microprocessor, the identifier in the corresponding interrupt controller to a value associated with the bootstrap processor.

11. The method of claim 9, further comprising:

modifying upper address bits of memory accesses by each processing core of the plurality of processing cores so that each processing core accesses a unique address space.

12. The method of claim 9, wherein a holding register of the microprocessor designates the first or second mode of operation for the plurality of processing cores.

13. The method of claim 12, wherein the holding register is configured to receive a sensed evaluation of a fuse that is either blown or unblown.

14. The method of claim 12, wherein the holding register is configured to receive a value designating the mode from a boundary scan input.

15. The method of claim 9, wherein said determining the mode is performed in response to a reset of the microprocessor.

16. The method of claim 9, in the first mode, setting a flag in a respective register of each processing core of the plurality of processing cores to indicate the processing core is the bootstrap processor.

17. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising;

program code for specifying a plurality of processing cores configured to operate in first and second modes;

in the first mode, each of the plurality of processing cores concurrently operates as a bootstrap processor and concurrently executes a respective instance of a test program; and

in the second mode, only a single processing core of the plurality of processing cores operates as the bootstrap processor.

18. The computer program product of claim 17, wherein the at least one non-transitory computer usable medium is selected from the set of a disk, tape, or other magnetic, optical, or electronic storage medium.