Nonvolatile memory module having DRAM used as cache, computing system having the same, and operating method thereof

• US 9,971,697 B2
• Filed: 11/17/2016
• Issued: 05/15/2018
• Est. Priority Date: 12/14/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Chankyung, Kang, Uksong, Cha, Sanguhn, Seo, Sungyong, Cho, Youngjin, O, Seongil
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US15/354,354
• Publication Number:
  US 20170168931A1
• Time in Patent Office: 544 Days
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0853 Cache with multiport tag or data arrays
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 2212/1004 Compatibility, e.g. with legacy hardware
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/22 Employing cache memory using specific memory technology
• CPC Class Codes: G06F 2212/313 In storage device
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A nonvolatile memory module includes at least one nonvolatile memory, at least one nonvolatile memory controller configured to control the nonvolatile memory, at least one dynamic random access memory (DRAM) used as a cache of the at least one nonvolatile memory, data buffers configured to store data exchanged between the at least one DRAM and an external device, and a memory module control device configured to control the nonvolatile memory controller, the at least one DRAM, and the data buffers. The at least one DRAM stores a tag corresponding to cache data and compares the stored tag with input tag information to determine whether to output the cache data.

Claims

1. A nonvolatile memory module comprising:

at least one nonvolatile memory;

at least one nonvolatile memory controller configured to control the at least one nonvolatile memory;

at least one dynamic random access memory (DRAM) used as a cache of the at least one nonvolatile memory;

data buffers configured to store data exchanged between the at least one DRAM and an external device; and

a memory module control device configured to control the nonvolatile memory controller, the at least one DRAM, and the data buffers,

wherein the at least one DRAM stores a tag corresponding to cache data and compares the stored tag with input tag information to determine whether to output the cache data, and

wherein the at least one DRAM comprises;

at least one tag DRAM configured to store the stored tag; and

at least one data DRAM configured to store the cache data,

wherein the at least one tag DRAM comprises;

a first memory cell array configured to store the tag;

a first tag comparison circuit configured to compare the stored tag with the tag information to generate a match signal indicating a cache hit or cache miss; and

a first multiplexer deactivated when the first tag comparison circuit is activated.

2. The nonvolatile memory module of claim 1, wherein the at least one tag DRAM and the at least one data DRAM are implemented differently from each other.

3. The nonvolatile memory module of claim 1, wherein the at least one tag DRAM and the at least one data DRAM are implemented the same as each other.

4. The nonvolatile memory module of claim 3,

wherein the at least one data DRAM comprises:

a second memory cell array configured to store cache data corresponding to the stored tag;

a second tag comparison circuit; and

a second multiplexer deactivated when the second tag comparison circuit is activated and configured to determine whether to output the cache data in response to the match signal.

5. The nonvolatile memory module of claim 4, wherein the first and second tag comparison circuits and the first and second multiplexers are activated or deactivated by a fuse cutting or mode register setting.

6. The nonvolatile memory module of claim 4, wherein the at least one tag DRAM and the at least one data DRAM each comprise at least one pin associated with the match signal.

7. The nonvolatile memory module of claim 1, wherein the at least one DRAM includes a dual port DRAM.

8. The nonvolatile memory module of claim 7, wherein the at least one DRAM comprises:

first ports associated with an input/output path between the at least one DRAM and the data buffers; and

second ports associated with an input/output path between the at least one DRAM and the at least one nonvolatile memory controller.

9. The nonvolatile memory module of claim 7, wherein the at least one DRAM comprises:

a dedicated channel connected to the at least one nonvolatile memory controller to perform a flush function.

10. A nonvolatile memory module comprising:

at least one first nonvolatile memory;

at least one second nonvolatile memory;

a first nonvolatile memory controller configured to control the at least one first nonvolatile memory;

a second nonvolatile memory controller configured to control the at least one second nonvolatile memory;

first DRAMs connected to the first nonvolatile memory controller;

second DRAMs connected to the second nonvolatile memory controller;

data buffers connected to the first and second DRAMs; and

a memory module control device configured to generate a first command/address and a second command/address in response to a command/address from an external device, control the first and second nonvolatile memory controllers using the first command/address, and control the first and second DRAMs using the second command/address,

wherein each of the first and second DRAMs stores a cache and determines whether a cache hit is generated with respect to the cache, and

wherein each of the first and second DRAMs comprises;

at least one tag DRAM configured to store a tag corresponding to the cache; and

at least one data DRAM configured to store cache data,

wherein the at least one tag DRAM comprises;

a first memory cell array configured to store the tag;

a first tag comparison circuit configured to compare the stored tag with input tag information to generate a match signal indicating a cache hit or cache miss; and

a first multiplexer deactivated when the first tag comparison circuit is activated.

11. A nonvolatile memory module comprising:

at least one nonvolatile memory;

at least one nonvolatile memory controller configured to control the at least one nonvolatile memory;

at least one dynamic random access memory (DRAM) used as a cache of the at least one nonvolatile memory; and

a memory module control device configured to control the nonvolatile memory controller and the at least one DRAM and configured to output tag information to the at least one DRAM,

wherein the at least one DRAM stores a tag corresponding to cache data and compares the stored tag with the tag information from the memory module control device to determine whether a hit/miss is generated with respect to the cache, through the tag comparison; and

wherein the at least one DRAM comprises;

a plurality of DRAMs that store both the tag and the cache data,

wherein each of the plurality of DRAMs comprises;

a tag array configured to store the tag in first DRAM cells connected to a word line; and

a data array configured to store the cache data in second DRAM cells connected to the word line,

wherein the tag array stores tags corresponding to a plurality of caches according to a multi-way method,

wherein the data array stores cache data corresponding to the caches, and

wherein the tags and cache data corresponding to the caches are output by using a column to column delay time (tCCD).

12. The nonvolatile memory module of claim 11, further comprising data buffers configured to store data exchanged between the at least one DRAM and an external device and wherein the memory module control device is configured to control the data buffers.

13. The nonvolatile memory module of claim 12, wherein each of the plurality of DRAMs further comprises:

an address decoder configured to activate the word line in response to a row address;

a column decoder and sense amplifier configured to activate a first column selection line connected to the first DRAM cells and a second column selection line connected to the second DRAM cells in response to a column address and read the stored tag from the first DRAM cells or the cache data from the second DRAM cells;

a tag comparison circuit configured to compare the stored tag with the tag information from the memory module control device and generate a match signal indicating a cache hit or cache miss based on the comparison result; and

a multiplexer configured to output the cache data to one of the data buffers in response to the match signal.

14. The nonvolatile memory module of claim 13, wherein when a write request is received, a first match signal indicating the cache hit corresponding to the write request is generated by reading a first tag from the tag array and comparing the read tag with first tag information received with the first tag, and first cache data corresponding to the write request is stored in the data array in response to the first match signal.

15. The nonvolatile memory module of claim 13, wherein, when a read request is received, a second match signal indicating the cache hit corresponding to the read request is generated by reading a second tag from the tag array and comparing the read second tag with second tag information received with the second tag, and second cache data corresponding to the read request is read from the data array in response to the second match signal.

16. The nonvolatile memory module of claim 13, wherein the stored tag comprises a tag, cache data, and at least one parity for error correction of the tag.

17. The nonvolatile memory module of claim 13, wherein each of the tags further comprises dirty/clear information, and

wherein the dirty/clear information is output together with the cache data.