Data compression accelerator methods, apparatus and design structure with improved resource utilization
First Claim
1. An apparatus for compressing data, comprising:
- a plurality of hardware data compression accelerators that each process a respective stream of input phrases of said data during one or more of a write operation and a read operation of said data; and
a hash table shared by said plurality of hardware data compression accelerators during said one or more of said write operation and said read operation of said data, wherein said shared hash table records a location where a previous instance of a given input phrase of said data from said respective stream of input phrases of said data is stored and wherein multiple instances of said given input phrase are stored in said shared hash table as a single instance of said given input phrase to compress said data, wherein at least two of said plurality of hardware data compression accelerators substantially simultaneously share access to said shared hash table.
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Abstract
Methods, apparatus and design structures are provided for improving resource utilization by data compression accelerators. An exemplary apparatus for compressing data comprises a plurality of hardware data compression accelerators and a hash table shared by the plurality of hardware data compression accelerators. Each of the plurality of hardware data compression accelerators optionally comprises a first-in-first-out buffer that stores one or more input phrases. The hash table optionally records a location in the first-in-first-out buffers where a previous instance of an input phrase is stored. The plurality of hardware data compression accelerators can simultaneously access the hash table. For example, the hash table optionally comprises a plurality of input ports for simultaneous access of the hash table by the plurality of hardware data compression accelerators. A design structure for a data compression accelerator system is also disclosed.
18 Citations
20 Claims
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1. An apparatus for compressing data, comprising:
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a plurality of hardware data compression accelerators that each process a respective stream of input phrases of said data during one or more of a write operation and a read operation of said data; and a hash table shared by said plurality of hardware data compression accelerators during said one or more of said write operation and said read operation of said data, wherein said shared hash table records a location where a previous instance of a given input phrase of said data from said respective stream of input phrases of said data is stored and wherein multiple instances of said given input phrase are stored in said shared hash table as a single instance of said given input phrase to compress said data, wherein at least two of said plurality of hardware data compression accelerators substantially simultaneously share access to said shared hash table. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A hardware description language (HDL) design structure encoded on a non-transitory machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a data compression accelerator system, wherein said HDL design structure comprises:
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a plurality of hardware data compression accelerators that each process a respective stream of input phrases of said data during one or more of a write operation and a read operation of said data; and a hash table shared by said plurality of hardware data compression accelerators during said one or more of said write operation and said read operation of said data, wherein said shared hash table records a location where a previous instance of a given input phrase of said data from said respective stream of input phrases of said data is stored and wherein multiple instances of said given input phrase are stored in said shared hash table as a single instance of said given input phrase to compress said data, wherein at least two of said plurality of hardware data compression accelerators substantially simultaneously share access to said shared hash table. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification