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Multi-level security domain separation using soft-core processor embedded in an FPGA

  • US 9,971,910 B2
  • Filed: 01/22/2015
  • Issued: 05/15/2018
  • Est. Priority Date: 01/22/2015
  • Status: Active Grant
First Claim
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1. A system for performing operations on data in two different security domains,the system comprising a field-programmable gate array (FPGA),the FPGA comprising:

  • a first security domain having a first classification level, the first security domain comprising;

    first processing circuitry anda first soft-core processor, anda second security domain having a second classification level, the second security domain comprising;

    second processing circuitry anda second soft-core processor, andone or more security domain separation gates connected to the first security domain and to the second security domain, the one or more security domain separation gates configured;

    to receive first data from the first security domain and transmit the first data to the second security domain if the first data complies, during operation, with a first set of rules, andto receive second data from the second security domain and transmit the second data to the first security domain if the second data complies, during operation, with a second set of rules,the only data paths between the first security domain and the second security domain being through the one or more security domain separation gates, andthe second set of rules requiring that information to be transmitted from the first security domain to the second security domain be free of words and phrases indicating a likelihood that the information to be transmitted contains information of the second classification level.

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