Memory device for interruptible memory refresh

• US 9,972,376 B2
• Filed: 11/07/2013
• Issued: 05/15/2018
• Est. Priority Date: 11/07/2013
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cordero, Edgar R., Fernandez, Carlos A., Henderson, Joab D., Hovis, William P., Sabrowski, Jeffrey A., Saetow, Anuwat, Sethuraman, Saravanan
• Primary Examiner(s): Rojas, Midys
• Assistant Examiner(s): Choi, Charles J
• Application Number:
  US14/074,171
• Publication Number:
  US 20150127899A1
• Time in Patent Office: 1,650 Days
• Field of Search: None
• CPC Class Codes: G11C 11/40603 Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays

Abstract

A refresh command is received from a memory controller. An interruptible refresh containing multiple segment refreshes is initiated. The segment refreshes are separated by interrupt boundaries. A command is received before execution of a segment refresh. The first command is executed and execution of the first segment refresh is delayed at a first interrupt boundary. Alternatively, a first number of segment refreshes to execute is received from a memory controller. The received first number of segment refreshes is executed. A second number of segment refreshes to execute is received from a memory controller. The received second number of segment refreshes is executed. No segment refreshes are executed between the execution of the first number of segment refreshes and the execution of the second number of segment refreshes.

Claims

1. A method for refreshing a DRAM, performed by the DRAM, the method comprising:

receiving, by the DRAM and from a memory controller, a refresh command in response to expiration of a refresh timer;

initiating, by the DRAM, an interruptible refresh in response to the receiving the refresh command, the interruptible refresh comprising execution of a plurality of segment refreshes, the execution of each of the plurality of segment refreshes separated by interrupt boundaries, the plurality of segment refreshes comprising a first segment refresh and a second segment refresh, the first segment refresh and the second segment refresh separated by a first interrupt boundary, the interruptible refresh configured to complete without receiving further refresh commands;

receiving, by the DRAM during execution of the interruptible refresh, a first command during the first segment refresh;

completing, by the DRAM, the first segment refresh;

executing, by the DRAM and in response to receiving the first command, the first command at the first interrupt boundary on a region of the DRAM where the second segment refresh is to be executed; and

continuing, by the DRAM and after execution of the first command, the interruptible refresh with the second segment refresh.

2. The method of claim 1, wherein the DRAM is a singular DRAM module.

3. A method for refreshing one or more modules of DRAM, the modules communicatively coupled to one or more memory controllers, the method comprising:

receiving, by a DRAM, a first command, the first command received from a first memory controller, the first command instructing the DRAM to refresh two or more stored values within the DRAM;

beginning, by the DRAM, refresh of the stored values in response to receiving the first command;

receiving, by the DRAM during execution of the refresh command and after beginning the refresh, a second command, the second command received from the first memory controller, the second command not instructing refresh of the stored values;

delaying, by the DRAM before completion of the refresh command, the refresh in response to receiving the second command;

executing, by the DRAM, the second command on a region of the DRAM where segment refresh is to be executed; and

continuing, by the DRAM and after execution of the second command, the refresh.

4. The method of claim 3, wherein the second command is a read command, and wherein the executing the second command comprises:

reading one or more values from the DRAM.

5. The method of claim 3, wherein the second command is a write command, and wherein the executing the second command comprises:

writing one or more values to the DRAM.

6. The method of claim 3, wherein the first command instructs the DRAM to refresh all of the stored values within the DRAM.

7. A method for refreshing one or more 3D stacked memory devices, the devices communicatively coupled to one or more memory controllers, the method comprising:

receiving, by a 3D stacked memory device, a first command, the first command received from a first memory controller, the first command instructing the 3D stacked memory device to refresh the stored values within the 3D stacked memory device;

beginning, by the 3D stacked memory device, refresh of the stored values in response to receiving the first command;

receiving, by the 3D stacked memory device and after beginning the refresh, a second command, the second command received from the first memory controller, the second command not instructing refresh of the stored values;

delaying, by the 3D stacked memory device, the refresh in response to receiving the second command;

executing, by the 3D stacked memory device, the second command on a region of the 3D stacked memory where segment refresh is to be executed; and

continuing, by the 3D stacked memory device and after execution of the second command, the refresh.

8. The method of claim 7, wherein the second command is a read command, and wherein the executing the second command comprises:

reading one or more values from the 3D stacked memory device.

9. The method of claim 7, wherein the second command is a write command, and wherein the executing the second command comprises:

writing one or more values to the 3D stacked memory device.

10. The method of claim 7, wherein the first command instructs the 3D stacked memory device to refresh all of the stored values within the 3D stacked memory device.