Memory with output control

• US 9,972,381 B1
• Filed: 01/11/2018
• Issued: 05/15/2018
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Oh, HakJune, Pyeon, Hong Beom, Kim, Jin-Ki
• Primary Examiner(s): Auduong, Gene
• Application Number:
  US15/868,219
• Publication Number:
  US 20180137912A1
• Time in Patent Office: 124 Days
• Field of Search: 36518511, 36518512, 36518517, 36518533, 36518905, 36518915, 365221, 3652331, 365239
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Claims

1. A flash memory device comprising:

a flash memory comprising a plurality of erasable blocks, each erasable block comprising a plurality of pages, each page comprising a plurality of flash memory cells;

a clock input port configured to receive a clock signal;

at least one common data interface configured to transfer command data, address data, input data and output data, wherein at least one of command data, address data, input data and output data is transferred in synchronization with both rising and falling edges of the clock signal when the flash memory device is in a double data rate configuration;

a control input port configured to receive a control signal, wherein a transition of the control signal from an inactive state to an active state indicates a beginning of command data being received at the at least one common data interface;

a control circuitry configured to execute a page program operation to store the input data on a selected page, and to execute a read operation to retrieve the output data from the flash memory cells in accordance to the command data and address data received at the at least one common data interface; and

a status register configured to indicate a status of the flash memory device.

2. The flash memory device as claimed in claim 1, wherein the command data is latched at the first rising edge of the clock signal after the transition of the control signal.

3. The flash memory device as claimed in claim 1, wherein the status register is further configured to provide a result of the page program operation after the page program operation is completed.

4. The flash memory device as claimed in claim 1, further comprising a clock output port configured to transmit a clock output signal synchronized with the output data when the flash memory device is in the double data rate configuration.

5. The flash memory device as claimed in claim 4, further comprising a delay lock loop (DLL) to synchronize the clock output signal with the clock signal.

6. The flash memory device as claimed in claim 1, wherein a transition of the control signal from the active state to the inactive state indicates an end of the transfer of the at least one of command data, address data, input data and output data.

7. The flash memory device as claimed in claim 1, wherein the flash memory device is a NAND flash memory device.

8. The flash memory device as claimed in claim 1, wherein the flash memory device is a NOR flash memory device.

9. The flash memory device as claimed in claim 1, wherein the flash memory cell is a single-level-cell.

10. The flash memory device as claimed in claim 1, wherein the flash memory cell is a multi-level-cell.

11. The flash memory device as claimed in claim 1, wherein the at least one common data interface comprises a single-bit serial data input and output.

12. The flash memory device as claimed in claim 1, wherein the at least one common data interface comprises multi-bit serial data input and output.

13. The flash memory device as claimed in claim 1, wherein the control circuitry is configured to perform the read operation during a time period that overlaps with a time period for the page program operation.

14. The flash memory device as claimed in claim 1, further comprising a second control input port configured to receive a reset signal, wherein the status register is configured to be reset when the reset signal is received at the second control input port.

15. The flash memory device as claimed in claim 1, further comprising an error correcting code (ECC) configured to be utilized during the page program operation.

16. The flash memory device as claimed in claim 1, wherein the control circuitry is configured to automate the page program operation including an internal verification.

17. A method of operating a flash memory device, the flash memory device comprising a clock input port, a control input port, at least one common data interface, a control circuitry, a status register, and a plurality of flash memory arrays, each flash memory array comprising a plurality of erasable blocks, each erasable block comprising a plurality of pages, each page comprising a plurality of flash memory cells, the method comprising:

providing a clock signal to the clock input port;

transferring command data, address data, input data and output data to and from the at least one common data interface, wherein at least one of command data, address data, input data and output data is transferred in synchronization with both rising and falling edges of the clock signal when the flash memory device is in a double data rate configuration;

providing a control signal to the control input port, wherein a first transition of the control signal from an inactive state to an active state indicates a beginning of command data being provided at the at least one common data interface;

providing a page program command to the control circuitry to perform a page program operation to store the input data on a selected page of the flash memory device;

providing a read command to retrieve the output data from the flash memory cells; and

providing a read status command to access the status register and determine a status of the flash memory device.

18. The method of claim 17, further comprising receiving a result of the page program operation after the page program operation is completed.

19. The method of claim 17, further comprising, receiving a clock output signal from a clock output port of the flash memory device in synchronization with the output data when the flash memory device is in the double data rate configuration.

20. The method of claim 17, wherein a second transition of the control signal from the active state to the inactive state indicates an end of the transfer of the at least one of command data, address data, input data and output data.

21. The method of claim 17, wherein the providing a read command occurs during a time period that overlaps with a time period for the page program operation.