Accelerating programming of a flash memory module

• US 9,972,393 B1
• Filed: 07/03/2014
• Issued: 05/15/2018
• Est. Priority Date: 07/03/2014
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Segal, Avigdor
• Primary Examiner(s): Thai, Tuan
• Assistant Examiner(s): Sain, Gautam
• Application Number:
  US14/323,889
• Time in Patent Office: 1,412 Days
• Field of Search: 711103
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written

Abstract

According to an embodiment of the invention there is provided a method for accelerating programming of data, the method may include receiving multiple input data units that were sent from a host computer; wherein the input data units may include first and second input data units; first level programming the first input data units to cache memory pages and first level programming the second input data units to first level target memory pages; and applying a copy back operation that comprises retrieving the first input data units from the cache memory pages and second level programming the first input data units to second level target memory pages; wherein any target page out of the first level target pages and the second level target pages differs from a cache memory page; and wherein the first level programming is faster than the second level programming.

Claims

1. A method for accelerating programming of data, comprising:

receiving multiple input data units that were sent from a host computer;

wherein the input data units comprise first and second input data units;

most significant bit (MSB) programming the first input data units to cache memory pages and MSB programming the second input data units to first level target memory pages; and

applying a copy back operation that comprises retrieving the first input data units from the cache memory pages and least significant bit (LSB) programming the retrieved first input data units to second level target memory pages;

wherein any target page out of the first level target memory pages and the second level target memory pages differs from a cache memory page;

wherein the MSB programming is faster than the LSB programming;

wherein the input data units further comprise third input data units;

wherein the method further comprises MSB programming the third input data units to additional cache memory pages;

wherein the applying of the copy back operation further comprises retrieving the third input data units from the additional cache memory pages and third level programming the third input data units to third level target memory pages; and

wherein the third level programming differs by speed from the MSB and LSB programming.

2. The method according to claim 1, wherein the MSB programming of the first and second input data units occur in parallel to each other.

3. The method according to claim 1, wherein the MSB programming of the first and second input data units occur in a partially overlapping manner.

4. The method according to claim 1, further comprising preventing further programming of any input data unit after the input data unit is programmed to a target page.

5. The method according to claim 1, wherein a ratio between an overall number of dies performing Copy Back and an overall number of dies caching exceeds one.

6. The method according to claim 1, wherein a ratio between an overall number of dies performing Caching and an overall size of dies performing Copy Back is a fraction of a ratio between programming speeds of the MSB and the LSB programming.

7. The method according to claim 6, wherein the fraction is one half.

8. The method according to claim 1, wherein the cache memory pages and the first level target pages are MSB pages.

9. The method according to claim 8, wherein the second level target pages are LSB pages.

10. The method according to claim 9, wherein the MSB programming of the first and second input data units occur in parallel to each other.

11. The method according to claim 9, wherein the MSB programming of the second input data units and the first input data units occur in a partially overlapping manner.

12. The method according to claim 1, wherein the receiving the multiple input data units from the host computer includes continuously receiving additional ones of the multiple input data units while MSB programming the first input data units.

13. A method for accelerating programming of data, comprising:

receiving multiple input data units by a memory controller and from a host computer;

wherein the input data units comprises first and second input data units;

instructing a programming circuit of a flash memory module to perform most significant bit (MSB) programming the first input data units to cache memory pages of the flash memory module and to perform MSB programming the second input data units to first level target memory pages of the flash memory module; and

instructing a copy back circuit of the flash memory module to apply a copy back operation that comprises retrieving the first input data units from the cache memory pages and least significant bit (LSB) programming the retrieved first input data units to second level target memory pages;

wherein any target page out of the first level target memory pages and the second level target memory pages differs from a cache memory page;

wherein the MSB programming is faster than the LSB programming;

wherein the input data units further comprise third input data units;

wherein the method further comprises MSB programming the third input data units to additional cache memory pages;

wherein the applying of the copy back operation further comprises retrieving the third input data units from the additional cache memory pages and third level programming the third input data units to third level target memory pages; and

wherein the third level programming differs by speed from the MSB and LSB programming.

14. The method according to claim 13, further comprising allocating cache memory pages and target pages.

15. The method according to claim 14, wherein the allocating is responsive to programming speeds of the MSB and LSB programming.

16. The method according to claim 13, wherein the cache memory pages and the first level target pages are MSB pages, and wherein the second level target pages are LSB pages.

17. A non-transitory computer readable medium that stores instructions that once executed by a computer causes the computer to execute the stages of:

receiving multiple input data units that were sent from a host computer;

wherein the input data units comprises first and second input data units;

most significant bit (MSB) programming the first input data units to cache memory MSB pages and MSB programming the second input data units to MSB target memory pages; and

applying a copy back operation that comprises retrieving the first input data units from the cache memory MSB pages and least significant bit (LSB) programming the retrieved first input data units to LSB target memory pages;

wherein any target page out of the MSB target memory pages and the LSB target memory pages differs from a cache memory MSB page;

wherein the MSB programming is faster than the LSB programming; and

wherein a ratio between an overall number of dies performing the caching and an overall size of dies performing the copy back operation is a fraction of a ratio between programming speeds of the MSB and the LSB programming.

18. A memory controller, comprising;

a control unit; and

an interface;

wherein the interface is arranged to receive multiple input data units from a host computer;

wherein the input data units comprises first and second input data units;

wherein the control unit is arranged to;

instruct a programming circuit of a flash memory module to perform most significant bit (MSB) programming the first input data units to cache memory pages of the flash memory module and to perform MSB programming of the second input data units to first level target memory pages of the flash memory module; and

instruct a copy back circuit of the flash memory module to apply a copy back operation that comprises retrieving the first input data units from the cache memory pages and least significant bit (LSB) programming the retrieved first input data units to second level target memory pages;

wherein any target page out of the first level target memory pages and the second level target memory pages differs from a cache memory page;

wherein the MSB programming is faster than the LSB programming; and

wherein a ratio between an overall number of dies performing the copy back operation and an overall number of dies caching exceeds one.

19. The memory controller according to claim 18, wherein the cache memory pages and the first level target pages are MSB pages, and wherein the second level target pages are LSB pages.

20. A flash memory module, comprising:

an interface;

a copy back circuit;

a programming circuit; and

flash memory pages;

wherein the interface is arranged to receive multiple input data units from a memory controller;

wherein the input data units comprise first and second input data units;

wherein the programming circuit is arranged to perform most significant bit (MSB) programming the first input data units to cache memory pages of the flash memory module and to perform MSB programming of the second input data units to first level target memory pages of the flash memory module; and

wherein the copy back circuit is arranged to apply a copy back operation that comprises retrieving the first input data units from the cache memory pages and least significant bit (LSB) programming the retrieved first input data units to second level target memory pages;

wherein any target page out of the first level target memory pages and the second level target memory pages differs from a cache memory page;

wherein the MSB programming is faster than the LSB programming; and

wherein a ratio between an overall number of dies performing the copy back operation and an overall number of dies caching exceeds one.