Level shifter circuit and associated memory device

• US 9,972,394 B2
• Filed: 03/31/2017
• Issued: 05/15/2018
• Est. Priority Date: 08/30/2016
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Conte, Antonino, Paolino, Carmelo, Perroni, Maurizio Francesco, Polizzi, Salvatore
• Primary Examiner(s): Lam, David
• Application Number:
  US15/476,003
• Publication Number:
  US 20180061495A1
• Time in Patent Office: 410 Days
• Field of Search: 36518523, 36518911, 36518909, 326 62- 63, 326 68
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A level shifter circuit is designed to shift an input signal that switches within a first voltage range to supply an output signal that switches within a second voltage range, higher than the first voltage range. A first inverter stage has an input receiving the input signal and also has an output. A first capacitive element is connected between the output of the first input inverter stage and a first holding node. A latch stage is connected between the first holding node and a second holding node that is coupled to an output terminal, on which the output signal is present. The first input inverter stage is designed to operate in the first voltage range, and the latch stage is designed to operate in the second voltage range.

Claims

1. A level shifter circuit comprising:

a first input inverter stage having an input configured to receive an input signal that switches within a first voltage range, wherein the first input inverter stage is designed to operate in the first voltage range;

a first capacitive element coupled between an output of the first input inverter stage and a first holding node;

a latch stage coupled between the first holding node and a second holding node, the second holding node serving as an output terminal configured to supply an output signal that switches within a second voltage range that is higher than the first voltage range, wherein the latch stage is designed to operate in the second voltage range; and

an initialization stage coupled to the second holding node and configured to define an initial operating state of the latch stage, wherein the initialization stage comprises an initialization transistor having a current path coupled between the second holding node and a reference terminal set at an initialization voltage, and having a gate configured to receive a reset signal.

2. The circuit according to claim 1, wherein the second voltage range has a lower-limit voltage and an upper-limit voltage;

wherein the latch stage has biasing reference inputs configured to receive the lower-limit voltage and the upper-limit voltage;

wherein the latch stage is configured to hold voltage values on the first holding node and the second holding node, alternatively equal to the lower-limit voltage or to the upper-limit voltage; and

wherein the latch stage is configured to switch its operating state following upon switching of the input signal.

3. The circuit according to claim 1, wherein the latch stage comprises:

a first latch inverter having an input coupled to the first holding node and an output coupled to the second holding node; and

a second latch inverter having an input coupled to the output of the first latch inverter and an output coupled to the input of the first latch inverter, wherein the first and second latch inverters are configured to operate in the second voltage range.

4. The circuit according to claim 1, wherein the latch stage comprises:

a first PMOS transistor having a gate coupled to the second holding node and a current path coupled between a high voltage node and the first holding node, the high voltage node configured to carry a voltage at an upper end of the second voltage range;

a first NMOS transistor having a gate coupled to the second holding node and a current path coupled between the first holding node and a low voltage node, the low voltage node configured to carry a voltage at a lower end of the second voltage range;

a second PMOS transistor having a gate coupled to the first holding node and a current path coupled between the high voltage node in the second holding node; and

a second NMOS transistor having a gate coupled to the first holding node and a current path coupled between the second holding node and the low voltage node.

5. The circuit according to claim 1 , wherein the initialization stage is configured to control initialization of the second holding node at an initialization voltage to define an initial operating state of the latch stage.

6. The circuit according to claim 1, further comprising:

a second input inverter stage having an input configured to receive a complementary input signal that switches with the first voltage range, the complementary input signal being a complement of the input signal; and

a second capacitive element coupled between an output of the second input inverter stage and the second holding node.

7. The circuit according to claim 1, wherein the first capacitive element comprises a MOS transistor having current-conduction terminals connected together, to a respective bulk terminal, and further to the first holding node, the MOS transistor also having a gate terminal coupled to the output of the first input inverter stage.

8. The circuit according to claim 1, further comprising:

a first output buffer having an input coupled to the first holding node; and

a second output buffer having an input coupled to the second holding node, an output of the second output buffer being the complement of an output of the first output buffer.

9. The circuit according to claim 1, wherein the input signal is configured to switch between a lower value and an upper value of the first voltage range, and the output signal is configured to switch, between an upper-limit voltage and a lower-limit voltage of the second voltage range.

10. A level shifter circuit comprising:

a first input inverter stage having an input configured to receive an input signal that switches within a first voltage range and an output coupled to a first holding node, wherein the first input inverter stage is configured to operate in the first voltage range;

a latch stage coupled between the first holding node and a second holding node, the second holding node serving as an output terminal configured to supply an output signal that switches within a second voltage range that is higher than the first voltage range, wherein the latch stage is configured to operate in the second voltage range;

a second input inverter stage having an input configured to receive a complementary input signal that switches with the first voltage range, the complementary input signal being a complement of the input signal, the second input inverter stage also having an output coupled to the second holding node, wherein the second input inverter stage is configured to operate in the first voltage range; and

an initialization stage coupled to the second holding node and configured to define an initial operating state of the latch stage, wherein the initialization stage comprises an initialization transistor having a current path coupled between the second holding node and a reference terminal set at an initialization voltage, and having a gate configured to receive a reset signal.

11. The circuit according to claim 10, further comprising:

a first capacitive element coupled between the output of the first input inverter stage and the first holding node; and

a second capacitive element coupled between the output of the second input inverter stage and the second holding node.

12. A memory device, comprising:

a memory array including a plurality of memory cells arranged in rows and columns, the memory cells being coupled to respective wordlines and bitlines;

a decoder stage, configured to select and bias the wordlines or the bitlines as a function of address signals, wherein address signals comprise signals that switch within a first voltage range and the wordlines or bitlines are biased at a voltage within a second voltage range that is greater than first voltage range, wherein the decoder stage comprises a plurality of shifter circuits, each level shifter circuit comprising;

a first input inverter stage having an input configured to receive an address signal, wherein the first input inverter stage is configured to operate in the first voltage range;

a first capacitive element coupled between an output of the first input inverter stage and a first holding node;

a latch stage coupled between the first holding node and a second holding node, the second holding node serving as a terminal configured to supply a bias signal for use with a respective wordline or bitline, wherein the latch stage is configured to operate in the second voltage range; and

an initialization stage coupled to the second holding node and configured to define an initial operating state of the latch stage, wherein the initialization stage comprises an initialization transistor having a current path coupled between the second holding node and a reference terminal set at an initialization voltage, and having a gate configured to receive a reset signal.

13. The device according to claim 12, wherein the decoder stage comprises a plurality of selection transistors, which are operable for selectively coupling the wordlines or the bitlines to a driving stage, and wherein each shifter circuit is configured to generate the bias signal the selection transistor associated with the respective wordline or bitline.

14. The device according to claim 12, wherein each level shifter circuit further comprises an input shifter stage, configured to carry out a first level shifting of a selection signal, switching in a third voltage range that is lower than the first voltage range, the input shifter stage having an output coupled to the input of the first input inverter stage.

15. The device according to claim 12, wherein the initialization stage is configured to control initialization of the second holding node at an initialization voltage to define an initial operating state of the latch stage.

16. The device according to claim 12, further comprising an output buffer having an input coupled to the second holding node and an output configured to supply the bias signal.

17. The memory device according to claim 12, wherein each memory cell comprises a non-volatile memory cell.

18. The memory device according to claim 17, wherein each memory cell comprises a flash memory cell.

19. The memory cell according to claim 17, wherein each memory cell comprises a phase change memory (PCM) cell.

20. A method of operating a level shifter circuit, the method comprising:

receiving an input signal that switches within a first voltage range with a first input inverter having an output coupled to a first holding node;

latching a value of the input signal into a latch circuit coupled between the first holding node and a second holding node by using a first capacitive element coupled between the first input inverter and the first holding node, wherein the latch circuit comprises a first supply terminal and a second supply terminal;

supplying an output signal with the second holding node, wherein the second holding node switches within a second voltage range different than the first voltage range; and

initializing a state of the latch circuit by providing a reset signal to a control terminal of an initialization transistor having a current path coupled between the first supply terminal and the second holding node.

21. The method of claim 20, further comprising:

receiving a complementary input signal that switches within the first voltage range with a second input inverter having an output coupled to the second holding node, the second input inverter further comprising an output coupled to the second holding node via a second capacitive element.

22. The method of claim 21, wherein, the first input inverter comprises a third supply terminal and a fourth supply terminal, the method further comprising:

providing a first voltage to the first supply terminal;

providing a second voltage to the second supply terminal;

providing a third voltage to the third supply terminal; and

providing a fourth voltage to the fourth supply terminal, wherein the first, second, third and fourth voltages are different to each other, wherein the second voltage is higher than the first voltage, wherein the fourth voltage is higher than the third voltage, and wherein the second voltage is higher than the fourth voltage.

23. The method of claim 22, wherein:

the first voltage is higher or equal to 1.6 V;

the second voltage is higher or equal to 3.6 V;

the third voltage is equal to 0 V; and

the fourth voltage is equal to 1.8 V.