Semiconductor device having multiple thickness oxides

• US 9,972,540 B2
• Filed: 08/07/2016
• Issued: 05/15/2018
• Est. Priority Date: 08/07/2016
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cao, Qing, Cheng, Kangguo, Li, Zhengwen, Liu, Fei
• Primary Examiner(s): Mandala, Victor A
• Assistant Examiner(s): Rundio, Regan J
• Application Number:
  US15/230,443
• Publication Number:
  US 20180040515A1
• Time in Patent Office: 646 Days
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02332 into an oxide layer, e.g. changing SiO to SiON
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Method for fabricating semiconductor device comprising: forming a dummy gate on a first nitrided oxide layer and a non-nitrided oxide layer; nitridizing an exposed section of the non-nitrided oxide layer to form a second nitrided oxide layer; forming an interlayer dielectric on the first nitrided oxide layer and the second nitrided oxide layer; removing the dummy gate from the first nitrided oxide layer to form a first opening with the first nitrided oxide layer exposed in the first opening; removing the dummy gate from the non-nitrided oxide layer to form a second opening with a non-nitrided portion of oxide layer exposed in the second opening; removing the non-nitrided portion of the oxide layer; forming a first dielectric layer and first metal gate material in the first opening; and forming a second dielectric layer and second metal gate material in the second opening.

Claims

1. Method for fabricating semiconductor device comprising:

forming an oxide layer on a semiconductor substrate;

nitridizing a first portion of the oxide layer to form a first nitrided oxide layer;

forming a dummy gate on the first nitrided oxide layer and on a second portion of the oxide layer;

nitridizing an exposed section of the second portion of the oxide layer not covered by the dummy gate on the second portion of the oxide layer to form a second nitrided oxide layer;

forming an interlayer dielectric on the first nitrided oxide layer and on the second nitrided oxide layer;

removing the dummy gate from the first nitrided oxide layer to form a first opening with the first nitrided oxide layer exposed in the first opening;

removing the dummy gate from the second portion of the oxide layer to form a second opening with a non-nitrided section of the second portion of the oxide layer exposed in the second opening;

removing the non-nitrided section of the second portion of the oxide layer;

forming a first dielectric layer in the first opening and filling a remainder of the first opening with a first metal gate material; and

forming a second dielectric layer in the second opening and filling a remainder of the second opening with a second metal gate material.

2. The method of claim 1 further comprising forming spacers on the first nitrided oxide layer, forming a source and a drain in the semiconductor substrate underneath the first nitrided oxide layer, forming spacers on the second nitrided oxide layer and forming a source and a drain in the semiconductor substrate underneath the second nitrided oxide layer.

3. The method of claim 1 wherein the first dielectric layer is in contact with the first nitrided oxide layer and the second dielectric layer is in contact with the semiconductor substrate.

4. The method of claim 3 wherein the first nitrided oxide layer in contact with the first dielectric layer and the first dielectric layer together have a first thickness and the second dielectric layer in contact with the semiconductor substrate has a second thickness such that the first thickness is greater than the second thickness.

5. The method of claim 1 wherein nitridizing the first portion of the oxide layer further includes protecting the second portion of the oxide layer during the nitridizing from being nitrided.

6. The method of claim 1 wherein nitridizing the first portion of the oxide layer is by a nitrogen plasma process.

7. The method of claim 1 wherein nitridizing the exposed section of the second portion of the oxide layer is by a nitrogen plasma process.

8. The method of claim 1 wherein removing the non-nitrided section of the second portion of the oxide layer further includes protecting the first nitrided oxide layer during the removing.

9. The method of claim 1 wherein the first dielectric layer and the second dielectric layer are continuous on sides and a bottom of the first opening and the second opening, respectively.

12. The method of claim 1 wherein the first dielectric layer is in contact with the first nitrided oxide layer and the second dielectric layer is in contact with the semiconductor substrate such that there is not a nitrided oxide layer between the second dielectric layer and the semiconductor substrate.

13. The method of claim 12 wherein the first nitrided oxide layer in contact with the first dielectric layer and the first dielectric layer together have a first thickness and the second dielectric layer in contact with the semiconductor substrate has a second thickness such that the first thickness is greater than the second thickness.

10. Method for fabricating semiconductor device comprising:

forming an oxide layer on a semiconductor substrate;

nitridizing a first portion of the oxide layer to form a first nitrided oxide layer while simultaneously protecting a second portion of the oxide layer during the nitridizing from being nitrided;

forming a dummy gate on the first nitrided oxide layer and the second portion of the oxide layer;

nitridizing an exposed section of the second portion of the oxide layer not covered by the dummy gate on the second portion of the oxide layer to form a second nitrided oxide layer;

forming spacers on the first nitrided oxide layer adjacent to the dummy gate on the first nitrided oxide layer;

forming spacers on the second nitrided oxide layer adjacent to the dummy gate on the second portion of the oxide layer;

forming an interlayer dielectric on the first nitrided oxide layer and the second nitrided oxide layer;

removing the dummy gate from the first nitrided oxide layer to form a first opening with the first nitrided oxide layer exposed in the first opening;

removing the dummy gate from the second portion of the oxide layer to form a second opening with a non-nitrided section of the second portion of the oxide layer exposed in the second opening;

removing the non-nitrided section of the second portion of the oxide layer;

forming a first dielectric layer in the first opening and filling a remainder of the first opening with a first metal gate material; and

forming a second dielectric layer in the second opening and filling a remainder of the second opening with a second metal gate material.

11. The method of claim 10 further comprising forming a source and a drain in the semiconductor substrate underneath the first nitrided oxide layer and forming a source and a drain in the semiconductor substrate underneath the second nitrided oxide layer.

14. The method of claim 10 wherein nitridizing the first portion of the oxide layer is by a nitrogen plasma process.

15. The method of claim 10 wherein nitridizing the exposed section of the second portion of the oxide layer is by a nitrogen plasma process.

16. The method of claim 10 wherein removing the non-nitrided section of the second portion of the oxide layer further includes protecting the first nitrided oxide layer during the removing.

17. The method of claim 10 wherein the first dielectric layer and the second dielectric layer are continuous on sides and a bottom of the first opening and the second opening, respectively.

18. A semiconductor device comprising:

a semiconductor substrate comprising a first portion and a second portion;

a first nitrided oxide layer having a first nitride oxide thickness formed on the first portion of the semiconductor substrate, a gate on the first nitrided oxide layer and an interlevel dielectric layer on the first nitrided oxide layer and adjacent to the gate, the gate comprising a first dielectric layer and a first metallic gate material;

a second nitrided oxide layer having a second nitrided oxide thickness on the second portion of the semiconductor substrate and having a gap where the second nitrided oxide layer is not on the semiconductor substrate, a gate positioned in the gap so as to be in contact with the semiconductor substrate, and the interlevel dielectric layer on the second nitrided oxide layer and adjacent to the gate, the gate comprising a second dielectric layer and a second metallic gate material;

wherein the first nitrided oxide layer has a greater amount of nitride than the second nitrided oxide layer.

19. The semiconductor device of claim 18 wherein the first nitrided oxide layer and the first dielectric layer together have a first undergate thickness and the second dielectric layer has a second undergate thickness such that the first undergate thickness is greater than the second undergate thickness.

20. The semiconductor device of claim 18 wherein the first dielectric layer and the second dielectric layer are continuous on sides and a bottom of the first metallic gate material and the second metallic gate material, respectively.