Vertical semiconductor devices including superlattice punch through stop layer and related methods

• US 9,972,685 B2
• Filed: 12/03/2015
• Issued: 05/15/2018
• Est. Priority Date: 11/22/2013
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Atomera Incorporated
• Inventors: Mears, Robert, Takeuchi, Hideki, Trautmann, Erwin
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): Ligai, Maria
• Application Number:
  US14/958,447
• Publication Number:
  US 20160099317A1
• Time in Patent Office: 894 Days
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.

Claims

1. A semiconductor device comprising:

a substrate;

a plurality of fins spaced apart on said substrate, each of said fins comprising

a lower semiconductor fin portion extending vertically upward from the substrate,

a plurality of spaced apart superlattice punch-through stop layers on the lower fin portion, each superlattice punch-through stop layer including a plurality of stacked groups of layers, each group of layers of the superlattice punch-through stop layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions,

a respective bulk semiconductor layer between adjacent superlattice punch-through stop layers, and

an upper semiconductor fin portion on an uppermost one of said superlattice punch-through stop layers and extending vertically upward therefrom;

source and drain regions at opposing ends of the fins; and

a gate overlying the fins.

2. The semiconductor device of claim 1 further comprising an insulating layer on the substrate surrounding the lower semiconductor fin portions.

3. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.

4. The semiconductor device of claim 1 wherein each base semiconductor portion comprises germanium.

5. The semiconductor device of claim 1 wherein the at least one non-semiconductor layer comprises oxygen.

6. The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

7. The semiconductor device of claim 1 wherein the gate comprises an oxide layer overlying the superlattice channel and a gate electrode overlying the oxide layer.

8. The semiconductor device of claim 1 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the non-semiconductor layer therebetween.

9. A semiconductor device comprising:

a substrate;

a plurality of fins spaced apart on said substrate, each of said fins comprising

a lower semiconductor fin portion extending vertically upward from the substrate,

a plurality of spaced apart superlattice punch-through stop layers on the lower fin portion, each superlattice punch-through stop layer including a plurality of stacked groups of layers, each group of layers of the superlattice punch-through stop layer comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions,

a respective bulk semiconductor layer between adjacent superlattice punch-through stop layers, and

an upper semiconductor fin portion on an uppermost one of said superlattice punch-through stop layers and extending vertically upward therefrom;

source and drain regions at opposing ends of the fins; and

a gate overlying the fins.

10. The semiconductor device of claim 9 further comprising an insulating layer on the substrate surrounding the lower semiconductor fin portions.

11. A semiconductor device comprising:

a substrate;

a plurality of fins spaced apart on said substrate, each of said fins comprising

a lower semiconductor fin portion extending vertically upward from the substrate,

a plurality of spaced apart superlattice punch-through stop layers on the lower fin portion, each superlattice punch-through stop layer including a plurality of stacked groups of layers, each group of layers of the superlattice punch-through stop layer comprising a plurality of stacked base germanium monolayers defining a base germanium portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base germanium portions, with the at least one non-semiconductor monolayer comprising a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen,

a respective bulk semiconductor layer between adjacent superlattice punch-through stop layers, and

an upper semiconductor fin portion on an uppermost one of said superlattice punch-through stop layers and extending vertically upward therefrom;

source and drain regions at opposing ends of the fins; and

a gate overlying the fins.

12. The semiconductor device of claim 11 further comprising an insulating layer on the substrate surrounding the lower semiconductor fin portions.