Semiconductor device and semiconductor device manufacturing method

• US 9,972,715 B2
• Filed: 07/26/2016
• Issued: 05/15/2018
• Est. Priority Date: 09/28/2015
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Ueno, Katsunori
• Primary Examiner(s): Picardat, Kevin M
• Application Number:
  US15/219,301
• Publication Number:
  US 20170092758A1
• Time in Patent Office: 658 Days
• Field of Search: 257 77, 257330, 257328
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

To more easily form a structure that mitigates the electrical field focus at the bottom portion of the trench gate and prevents decreases and variations in the gate threshold value (V_th), provided is a semiconductor device including a semiconductor substrate; a second semiconductor region with a second conduction type that is provided above the semiconductor substrate and includes a first semiconductor region with a first conduction type in a portion thereof; a third semiconductor region that is provided above the second semiconductor region and has a higher second conduction type impurity concentration than the second semiconductor region; and a gate trench that penetrates through the third semiconductor region and is provided on top of the first semiconductor region. The gate trench includes a gate insulating film provided on side walls and a bottom portion of the gate trench and a gate electrode provided in contact with the gate insulating film.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a second semiconductor region with a second conduction type that is provided above the semiconductor substrate and includes a first semiconductor region with a first conduction type in a portion thereof;

a third semiconductor region that is provided above the second semiconductor region and has a higher second conduction type impurity concentration than the second semiconductor region; and

a gate trench that penetrates through the third semiconductor region and is provided on top of the first semiconductor region, wherein

the gate trench includes a gate insulating film provided on side walls and a bottom portion of the gate trench and a gate electrode provided in contact with the gate insulating film,

the bottom portion of the gate trench is provided in direct contact with the first semiconductor region,

the width of the first semiconductor region extends from a bonding interface between the second semiconductor region and the third semiconductor region toward the semiconductor substrate side,

the bottom portion of the gate trench is provided lower than a bonding interface between the second semiconductor region and the third semiconductor region, and

the first semiconductor region has a portion that contacts the side walls of the gate trench, and

in the second semiconductor region, the second conduction type impurity concentration decreases from the bonding interface toward the semiconductor substrate side.

2. The semiconductor device according to claim 1, wherein

width of the gate trench is less than width of the first semiconductor region.

3. The semiconductor device according to claim 1, wherein

the first semiconductor region has a top portion that extends along the bonding interface.

4. The semiconductor device according to claim 1, further comprising:

a source trench that penetrates through the third semiconductor region, is provided at a position differing from a position of the gate trench, and includes electrode material.

5. The semiconductor device according to claim 4, further comprising:

a fourth semiconductor region with a first conduction type, between the substrate and the second semiconductor region; and

an embedded region that is provided at a distance from the source trench below the source trench, has a second conduction type impurity concentration that is higher than a second conduction type impurity concentration of the third semiconductor region, and is formed such that it straddles a boundary between the second semiconductor region and the fourth semiconductor region.

6. The semiconductor device according to claim 1, wherein

the semiconductor substrate is either a silicon carbide or nitride semiconductor.

7. The semiconductor device according to claim 1, wherein

the semiconductor device is used as a power semiconductor device with high withstand voltage.

8. A semiconductor device manufacturing method comprising:

epitaxially forming a second semiconductor region with a second conduction type on a semiconductor substrate;

epitaxially forming, on top of the second semiconductor region, a third semiconductor region that has a higher second conduction type impurity concentration than the second semiconductor region; and

forming a gate trench that penetrates through the third semiconductor region;

forming a first semiconductor region with a first conduction type in a portion of the second semiconductor region; and

forming a gate insulating film on side walls and a bottom portion of the gate trench and forming a gate electrode in contact with the gate insulating film,

wherein

the bottom portion of the gate trench is provided in direct contact with the first semiconductor region,

the width of the first semiconductor region extends from a bonding interface between the second semiconductor region and the third semiconductor region toward the semiconductor substrate side,

the bottom portion of the gate trench is provided lower than a bonding interface between the second semiconductor region and the third semiconductor region, and

the first semiconductor region has a portion that contacts the side walls of the gate trench, and

in the second semiconductor region, the second conduction type impurity concentration decreases from the bonding interface toward the semiconductor substrate side.

9. The semiconductor device manufacturing method according to claim 8, wherein

the forming the first semiconductor region includes forming the first semiconductor region by injecting impurities with the first conduction type into the portion of the second semiconductor region.

10. The semiconductor device manufacturing method according to claim 8, wherein

the first semiconductor region is formed after forming the gate trench, and

forming the first semiconductor region includes forming the first semiconductor region with the first conduction type in the portion of the second semiconductor region through the gate trench.