Thick FDSOI source-drain improvement

• US 9,972,721 B1
• Filed: 10/28/2016
• Issued: 05/15/2018
• Est. Priority Date: 10/28/2016
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Richter, Marcel, Pakfar, Ardechir, Muehlhoff, Armin
• Primary Examiner(s): Blum, David S
• Application Number:
  US15/337,368
• Publication Number:
  US 20180122956A1
• Time in Patent Office: 564 Days
• Field of Search: 438300
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

A method of forming a semiconductor device is disclosed including providing a semiconductor-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulating layer positioned on the semiconductor bulk substrate and a semiconductor layer positioned on the buried insulating layer, providing at least one metal-oxide semiconductor gate structure positioned above the semiconductor layer comprising a gate electrode and a spacer formed adjacent to the gate electrode, selectively removing an upper portion of the semiconductor layer so as to define recessed portions of the semiconductor layer and epitaxially forming raised source/drain regions on the recessed portions of the semiconductor layer.

Claims

1. A method of forming a semiconductor device, comprising:

providing a semiconductor-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulating layer positioned on said semiconductor bulk substrate and a semiconductor layer positioned on said buried insulating layer, said semiconductor layer having an initial thickness;

forming at least one metal-oxide semiconductor gate structure above said semiconductor layer comprising a gate electrode and a spacer formed adjacent to said gate electrode;

selectively removing an upper portion of said semiconductor layer so as to thereby define recessed portions of said semiconductor layer;

epitaxially forming raised source/drain regions on said recessed portions of said semiconductor layer; and

performing an annealing step so as to cause out-diffusion of dopant ions in said raised source/drain regions into said semiconductor layer to define doped semiconductor regions in portions of said semiconductor layer disposed beneath said raised source/drain regions, said doped semiconductor regions directly contacting said raised source/drain regions and said buried insulating layer.

2. The method of claim 1, wherein said initial thickness of said semiconductor layer is at least 5 nm.

3. The method of claim 1, wherein selectively removing said upper portion of said semiconductor layer comprises a performing at least one of a dry etching step or a wet etching step.

4. The method of claim 1, wherein said raised source/drain regions are formed adjacent to said spacer.

5. The method of claim 4, further comprising performing a lightly doped drain implantation process after forming said raised source/drain regions.

6. The method of claim 1, wherein said spacer comprises silicon nitride.

7. The method of claim 1, wherein said metal-oxide semiconductor gate structure is an N-type metal-oxide semiconductor gate structure or a P-type metal-oxide semiconductor gate structure.

8. The method of claim 7, wherein, for an N-type metal-oxide semiconductor gate structure, said semiconductor layer is a crystalline silicon layer, and wherein, for a P-type metal-oxide semiconductor structure, said semiconductor layer comprises a silicon-germanium material.

9. The method of claim 1, wherein said metal-oxide semiconductor gate structure further comprises a high temperature oxide layer positioned on said semiconductor layer, a metal gate layer positioned on said high temperature oxide layer and a polysilicon layer positioned on said metal gate layer.

10. The method of claim 9, wherein said spacer is provided adjacent to said metal gate layer and said polysilicon layer, and said spacer is positioned on said high temperature oxide layer.

11. The method of claim 1, wherein said semiconductor-on-insulator substrate is a fully depleted silicon-on-insulator substrate.

12. A method of forming a semiconductor device, comprising:

providing a semiconductor-on-insulator substrate comprising a semiconductor bulk substrate, a buried insulating layer positioned on said semiconductor bulk substrate and a semiconductor layer positioned on said buried insulating layer, said semiconductor layer having an initial thickness;

forming at least one metal-oxide semiconductor gate structure above said semiconductor layer comprising a gate electrode and a spacer formed adjacent to said gate electrode;

selectively removing an upper portion of said semiconductor layer so as to thereby define recessed portions of said semiconductor layer;

epitaxially forming raised source/drain regions on said recessed portions of said semiconductor layer;

implanting dopant ions into said raised source/drain regions; and

performing an annealing step so as to cause out-diffusion of said implanted dopant ions in said raised source/drain regions into said semiconductor layer to define doped semiconductor regions in portions of said semiconductor layer disposed beneath said raised source/drain regions, said doped semiconductor regions directly contacting said raised source/drain regions and said buried insulating layer.

13. The method of claim 12, wherein said initial thickness of said semiconductor layer is at least 5 nm.

14. The method of claim 12, wherein selectively removing said upper portion of said semiconductor layer comprises performing at least one of a dry etching step or a wet etching step.

15. The method of claim 12, wherein said raised source/drain regions are formed adjacent to said spacer.

16. The method of claim 15, further comprising performing a lightly doped drain implantation process after forming said raised source/drain regions.

17. The method of claim 12, wherein said metal-oxide semiconductor gate structure is an N-type metal-oxide semiconductor gate structure or a P-type metal-oxide semiconductor gate structure.

18. The method of claim 17, wherein, for an N-type metal-oxide semiconductor gate structure, said semiconductor layer is a crystalline silicon layer, and wherein, for a P-type metal-oxide semiconductor structure, said semiconductor layer comprises a silicon-germanium material.

19. The method of claim 12, wherein said metal-oxide semiconductor gate structure further comprises a high temperature oxide layer positioned on said semiconductor layer, a metal gate layer positioned on said high temperature oxide layer and a polysilicon layer positioned on said metal gate layer.

20. The method of claim 19, wherein said spacer is provided adjacent to said metal gate layer and said polysilicon layer, and said spacer is positioned on said high temperature oxide layer.