Field-effect transistor device with partial finger current sensing FETs

• US 9,973,183 B2
• Filed: 09/28/2015
• Issued: 05/15/2018
• Est. Priority Date: 09/28/2015
• Status: Active Grant

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Zhu, Lin, Varadarajan, Kamal Raj, Gaknoki, Yury
• Primary Examiner(s): Leja, Ronald W
• Application Number:
  US14/867,432
• Publication Number:
  US 20170093387A1
• Time in Patent Office: 960 Days
• Field of Search: 361 937
• CPC Class Codes: G01R 19/0092 measuring current only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G01R 19/16519 using FET's
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7826 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H02H 1/0007 concerning the detecting means in general G01R or other subclasses of G01; reed switches H01H71/2445
• CPC Class Codes: H02H 3/20 responsive to excess voltage
• CPC Class Codes: H03K 5/2472 using field effect transistors H03K5/2436 takes precedence

Abstract

A lateral semiconductor field-effect transistor (FET) device fabricated on a substrate includes a high-voltage main FET having interdigitated, elongated source and drain electrode fingers each of which is electrically connected to a respective interdigitated, elongated source and drain region disposed in the substrate. The FET device further includes first and second sense FETs each having a drain region in common with the high-voltage main FET. The sense FETS also include respective first and second elongated source electrode fingers each of which is electrically connected to respective first and second elongated source regions of the first and second sense FETs, respectively. The first and second elongated source electrode fingers are disposed length-wise adjacent to one of the elongated drain electrode fingers. The first elongated source finger has a first length, and the second elongated source finger has a second length, the second length being less than the first length.

Claims

1. A lateral semiconductor field-effect transistor (FET) device fabricated on a substrate comprising:

a high-voltage main FET having interdigitated, elongated source and drain electrode fingers each of which is electrically connected to a respective interdigitated, elongated source and drain region disposed in the substrate;

first and second sense FETs each having a drain region in common with the high-voltage main FET, and respective first and second elongated source electrode fingers each of which is electrically connected to respective first and second elongated source regions of the first and second sense FETs, respectively, the first and second elongated source electrode fingers being disposed length-wise adjacent to one of the elongated drain electrode fingers, the first elongated source finger having a first length, and the second elongated source finger having a second length, the second length being less than the first length;

wherein when the high-voltage main FET and the first and second sense FETs are in an on-state, first and second sense currents respectively flow through the first and second sense FETs, the first current being larger than the second current, with the sum of the first and second currents being a relatively small fraction of a drain current flowing through the high-voltage main FET.

2. The semiconductor FET device of claim 1 wherein a sum of the first length and the second length is less than or substantially equal to a length of the one of the elongated drain electrode fingers.

3. The semiconductor FET device of claim 1 further comprising a first sense resistor coupled in series with the first sense FET, and a second sense resistor coupled in series with the second sense FET, a first sense voltage being produced across the first sense resistor, and a second sense voltage being produced across the second sense resistor responsive to the first and second sense currents, respectively.

4. The semiconductor FET device of claim 3 wherein the first sense voltage and the second sense voltage are utilized for different functional limit purposes of the semiconductor FET device.

5. The semiconductor FET device of claim 1 further comprising a gate common to the high-voltage main FET and the first and second sense FETs.

6. The semiconductor FET device of claim 1 wherein the substrate is a first conductivity type, and the interdigitated, elongated source and drain regions are a second conductivity type, opposite to the first conductivity type.

7. The semiconductor FET device of claim 6 wherein the first conductivity type is P-type and the second conductivity type is N-type.

8. The semiconductor FET device of claim 6 further comprising a well region of the second conductivity type, the elongated drain regions being disposed in the well region.

9. The semiconductor FET device of claim 8 further comprising a plurality of buried regions of the first conductivity type disposed in the well region to define a plurality of lateral conduction channels.

10. The semiconductor field-effect transistor (FET) device of claim 8 wherein each of the elongated source regions is laterally separated from the well region by a portion of the substrate.

12. The integrated circuit of claim 1 wherein the first limit voltage is representative of a load limit through the high-voltage main FET.

11. An integrated circuit in a substrate comprising:

a high-voltage main field-effect transistor (FET) having interdigitated, elongated source and drain electrode fingers each of which is electrically connected to a respective interdigitated, elongated source and drain region disposed in the substrate, and a gate disposed over a region of the substrate that separates the source and drain regions;

first and second sense FETs each sharing a drain region of the high-voltage main FET, the first sense FET having a first elongated source electrode finger electrically connected to a first elongated source region of the first sense FET, the second sense FET having a second elongated source electrode finger electrically connected to a second elongated source region of the second sense FET, the first and second elongated source electrode fingers being disposed length-wise adjacent to one of the elongated drain electrode fingers, the first elongated source finger having a first length, and the second elongated source finger having a second length, the second length being less than the first length, wherein when the high-voltage main FET and the first and second sense FETs are in an on-state, first and second sense currents respectively flow through the first and second sense FETs;

first and second sense resistors coupled in series with the first and second sense FETs, respectively, a first sense voltage being produced across the first sense resistor, and a second sense voltage being produced across the second sense resistor, responsive to the first and second sense currents, respectively;

a multiplexer coupled to receive the first and second sense voltages at first and second inputs, respectively, the multiplexer also having an output and a switching control input; and

a first comparator having an output coupled to drive the switching control input of the multiplexer, and a pair of inputs coupled to compare the first sense voltage with a first limit voltage, when the first sense voltage is less than the first limit voltage the first sense voltage is provided at the output of the multiplexer, and when the first sense voltage exceeds the first limit voltage, the second sense voltage is provided at the output of the multiplexer.

13. The integrated circuit of claim 11 further comprising a second comparator having an output and a pair of inputs coupled to compare the output of the multiplexer with a second limit voltage, when the first sense voltage or second sense voltage provided at the output of the multiplexer is less than the second limit voltage, the first sense voltage or second sense voltage is provided at the output of the second comparator, and when the first sense voltage or second sense voltage provided at the output of the multiplexer exceeds the second limit voltage, the second limit voltage is provided at the output of the second comparator.

14. The integrated circuit of claim 13 wherein the second limit voltage is representative of a current limit of the high-voltage main FET.

15. The integrated circuit of claim 13 wherein a size of the first sense FET is proportional to the first length, and a size of the second sense FET is proportional to the second length, such that the first sense current is a first fraction, and the second sense current is a second fraction, of a drain current flowing through the high-voltage main FET when the high-voltage main FET and the first and second sense FETs are in an on-state.

16. The integrated circuit of claim 11 wherein a sum of the first length and the second length is less than or substantially equal to a length of the one of the elongated drain electrode fingers.

17. The integrated circuit of claim 11 wherein the first sense voltage and the second sense voltage are utilized for different functional limit purposes of the high-voltage main FET.

18. The integrated circuit of claim 17 wherein the first sense FET and first resistor are configured such that the first sense voltage provides maximum load current detection.

19. The integrated circuit of claim 17 wherein the second sense FET and second resistor are configured such that the second sense voltage provides current short circuit fault protection.