Protocol converter between CPCI bus and ISA bus and conversion method thereof

• US 9,973,347 B2
• Filed: 12/23/2016
• Issued: 05/15/2018
• Est. Priority Date: 02/05/2015
• Status: Active Grant

• Current Assignee: CRRC Qingdao Sifang Co. Ltd (CRRC Corp. Ltd.)
• Original Assignee: CRRC Qingdao Sifang Co. Ltd (CRRC Corp. Ltd.)
• Inventors: Zhang, Yawei, Zhu, Mengxiang, Qin, Jiaomei, Wang, Shuang
• Primary Examiner(s): Jaroenchonwanit, Bunjob
• Application Number:
  US15/390,287
• Publication Number:
  US 20170111184A1
• Time in Patent Office: 508 Days
• Field of Search: None
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: H04L 12/40 Bus networks
• CPC Class Codes: H04L 12/40169 Flexible bus arrangements arrangements for maintenance or administration involving management of faults; events, alarms H04L41/06; automatic restoration of network faults H04L41/0654
• CPC Class Codes: H04L 2012/40293 the transportation system being a train

Abstract

The present application relates to the technical field of field bus communication, and in particular to a protocol converter between a CPCI bus and an ISA bus and a conversion method thereof, which are suitable for communication between railway vehicle CPUs and vehicle bus MVB devices. The protocol converter comprises a CPCI local bus interface extension timing module, an ISA bus interface timing module, a CPCI bus matching ISA bus timing interface module, and a clock management module. The CPCI bus realizes communication with the ISA bus by the protocol converter. The traditional conversion bridge chips are replaced with the protocol converters without changing the traction controller structure and other devices in the system; the flexibility is high; and the functions are diverse. In addition, 8-bit data width or 16-bit data width of the ISA bus is supported, and the operation of an ISA bus device by a CPCI bus device in the form of IO or in the form of MEMORY is supported.

Claims

1. A protocol converter between a CPCI bus and an ISA bus, characterized in that, the protocol converter comprises a FPGA chip which is configured to execute a CPCI local bus interface extension timing module, an ISA bus interface timing module, a CPCI bus matching ISA bus timing interface module, and a clock management module;

the CPCI local bus interface extension timing module communicates with the CPCI bus by an address/data signal AD [31;

0], a command/byte enable signal C/BE [3;

0], a slave device get-ready signal TRDY, a data transfer stop signal STOP, a frame period signal FRAME, and a master device get-ready signal IRDY;

the ISA bus interface timing module communicates with the CPCI local bus interface extension timing module by a data enable signal S_DATA_VLD, an address enable signal ADDR_VLD, a read enable signal barx_rd, a write enable signal barx_wr, a byte enable signal S_CBE, a data signal D [31;

0] and an address signal A [31;

0];

the ISA bus interface timing module communicates with the ISA bus by a data signal SD, an address signal SA, a read/write IO device signal IOW/IOR, a read/write MEMORY device signal MEMR/MEMW, an address latch signal BALE;

the CPCI bus matching ISA bus timing interface module communicates with the CPCI local bus interface extension timing module by an interruption and reconnection signal USER_STOP; and

the clock management module provides an operation clock for the CPCI local bus interface extension timing module, the ISA bus interface timing module and the CPCI bus matching ISA bus timing interface module.

2. The protocol converter between the CPCI bus and the ISA bus according to claim 1, characterized in that, when the CPCI local bus interface extension timing module communicates with the CPCI bus, and when the CPCI bus accesses in the form of IO, a waiting signal S_WAIT is inserted in the read/write operation of the CPCI bus to control the slave device get-ready signal TRDY of the CPCI bus.

3. The protocol converter between the CPCI bus and the ISA bus according to claim 1, characterized in that, when the CPCI local bus interface extension timing module communicates with the CPCI bus, and when the CPCI bus accesses in the form of MEMORY, a data transfer stop signal STOP is inserted in the read/write operation of the CPCI bus;

and the data transfer stop signal STOP is interrupted by the interruption and reconnection signal USER_STOP.

4. A protocol conversion method for the CPCI bus and the ISA bus according to claim 1, comprising the following steps:

1) determining an access space IO/MEMORY of the CPCI bus, inserting the data transfer stop signal STOP when the CPCI bus accesses in the form of MEMORY, and inserting the waiting signal S_WAIT to wait for the ISA bus to get ready when the CPCI bus accesses in the form of IO;

2) according to the address enable signal ADDR_VLD, the read enable signal barx_rd, the write enable signal barx_wr and the byte enable signal S_CBE, determining an actual address signal SA and an access mode for the CPCI bus to access the ISA bus, wherein the access mode comprises a write operation and a read operation;

3) determining an address latch signal BALE of the ISA bus;

4) deciding byte data enabled in the 32-bit data according to the byte enable signal S_CBE; and

screening out corresponding 8-bit data or 16-bit data from an intermediate data buffering region BUFFER for data interaction with an MVB device;

5) determining the read/write IO device signal IOW/IOR or the read/write MEMORY device signal MEMR/MEMW according to the read/write signal pulse width specified by the ISA bus, and thus a main control CPU device accesses to the MVB device with the ISA bus interface by the CPCI bus in real time.

5. A protocol converter for communication between a CPCI bus and an ISA bus, comprising a processor and a memory, wherein the protocol converter is configured to:

1) determine an access space IO/MEMORY of the CPCI bus, and insert a data transfer stop signal STOP when the CPCI bus accesses in the form of MEMORY, or insert a waiting signal S_WAIT to wait for the ISA bus to get ready when the CPCI bus accesses in the form of IO;

2) according to an address enable signal ADDR_VLD, a read enable signal barx_rd, a write enable signal barx_wr and a byte enable signal S_CBE, determine an actual address signal SA and an access mode for the CPCI bus to access the ISA bus, wherein the access mode comprises a write operation and a read operation;

3) determine an address latch signal BALE of the ISA bus;

4) decide byte data enabled in 32-bit data according to the byte enable signal S_CBE; and

screen out corresponding 8-bit data or 16-bit data from an intermediate data buffering region BUFFER for data interaction with an MVB device; and

5) determine a read/write IO device signal IOW/IOR or a read/write MEMORY device signal MEMR/MEMW according to a read/write signal pulse width specified by the ISA bus, and thus a main control CPU device accesses to the MVB device with the ISA bus interface by the CPCI bus in real time.