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Protocol converter between CPCI bus and ISA bus and conversion method thereof

  • US 9,973,347 B2
  • Filed: 12/23/2016
  • Issued: 05/15/2018
  • Est. Priority Date: 02/05/2015
  • Status: Active Grant
First Claim
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1. A protocol converter between a CPCI bus and an ISA bus, characterized in that, the protocol converter comprises a FPGA chip which is configured to execute a CPCI local bus interface extension timing module, an ISA bus interface timing module, a CPCI bus matching ISA bus timing interface module, and a clock management module;

  • the CPCI local bus interface extension timing module communicates with the CPCI bus by an address/data signal AD [31;

    0], a command/byte enable signal C/BE [3;

    0], a slave device get-ready signal TRDY, a data transfer stop signal STOP, a frame period signal FRAME, and a master device get-ready signal IRDY;

    the ISA bus interface timing module communicates with the CPCI local bus interface extension timing module by a data enable signal S_DATA_VLD, an address enable signal ADDR_VLD, a read enable signal barx_rd, a write enable signal barx_wr, a byte enable signal S_CBE, a data signal D [31;

    0] and an address signal A [31;

    0];

    the ISA bus interface timing module communicates with the ISA bus by a data signal SD, an address signal SA, a read/write IO device signal IOW/IOR, a read/write MEMORY device signal MEMR/MEMW, an address latch signal BALE;

    the CPCI bus matching ISA bus timing interface module communicates with the CPCI local bus interface extension timing module by an interruption and reconnection signal USER_STOP; and

    the clock management module provides an operation clock for the CPCI local bus interface extension timing module, the ISA bus interface timing module and the CPCI bus matching ISA bus timing interface module.

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