Decision feedback equalizer and semiconductor integrated circuit
First Claim
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1. A decision feedback equalizer comprising:
- a comparator configured to output a constant voltage in a reset period and to output a differential voltage corresponding to differential input signals in an evaluation period;
a latch circuit configured to hold the differential voltage in the evaluation period; and
an adjuster configured to adjust a logical threshold of the latch circuit closer to the output constant voltage in the reset period.
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Abstract
A decision feedback equalizer includes a comparator configured to output a constant voltage in a reset period and to output a differential voltage corresponding to differential input signals in an evaluation period, a latch circuit configured to hold the differential voltage in the evaluation period, and an adjuster configured to adjust a logical threshold of the latch circuit closer to the output voltage in the reset period.
8 Citations
14 Claims
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1. A decision feedback equalizer comprising:
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a comparator configured to output a constant voltage in a reset period and to output a differential voltage corresponding to differential input signals in an evaluation period; a latch circuit configured to hold the differential voltage in the evaluation period; and an adjuster configured to adjust a logical threshold of the latch circuit closer to the output constant voltage in the reset period. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A semiconductor integrated circuit comprising:
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a decision feedback equalizer configured to decide data being sampled from differential input serial signals on the basis of a clock signal; a demultiplexer configured to output a parallel signal in accordance with an output signal of the decision feedback equalizer; and a clock recovery circuit configured to control a phase of the clock signal on the basis of a received signal, wherein the decision feedback equalizer includes; a comparator configured to output a constant voltage in a reset period and to output a differential voltage corresponding to the differential input signals in an evaluation period, a latch circuit configured to hold the differential voltage in the evaluation period, and an adjuster configured to adjust a logical threshold of the latch circuit closer to the output constant voltage in the reset period.
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Specification