Self-test solution for delay locked loops

• US 9,977,077 B1
• Filed: 08/09/2016
• Issued: 05/22/2018
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Inventors: Raffian, Edzel Gerald Dela Cruz
• Primary Examiner(s): Assouad, Patrick
• Assistant Examiner(s): Zhang, Haidong
• Application Number:
  US15/232,801
• Time in Patent Office: 651 Days
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/50012 of timing

Abstract

A built-in self test (BIST) circuit and method is provided to test a first and a second DLL. The first DLL has a first delay input, a first clock input disposed to receive a clock input signal, and a first clock output that provides a first clock output signal delayed in comparison with the clock input signal. The second DLL has a second delay input, a second clock input disposed to receive the clock input signal, and a second clock output signal delayed in comparison with the clock input signal. The BIST circuitry provides a first delay amount over the first delay input creating a start offset between the first and second clock output signals. If the first DLL is functioning properly the start offset between the output signals should remain unchanged even after the BIST circuitry provides an additional common delay amount to the first and second delay inputs.

Claims

1. A built-in self-test system for use in circuitry having two or more delay locked loops (DLLs), comprising:

a first DLL having a first delay input, a first clock input disposed to receive a clock input signal and a first clock output providing a first clock output signal delayed in comparison with the clock input signal;

a second DLL having a second delay input, a second clock input disposed to receive the clock input signal and a second clock output providing a second clock output signal delayed in comparison with the clock input signal;

a test controller provides a first delay amount over the first delay input of the first DLL to create a start offset between the first clock output signal and the second clock output signal and further provides at least one common delay amount to both the first delay input of the first DLL and the second delay input of the second DLL;

a sample component that creates a test dataset by sampling the second clock output signal from the second DLL during at least one edge of the first clock output signal from the first DLL; and

a compare component that performs a comparison of the test dataset with a comparison dataset and produces a comparison result from a comparison of the first clock output signal from the first DLL with the second clock output signal from the second DLL.

2. The system of claim 1 wherein the circuitry having two or more DLLs is selected from a set of circuits including:

a double-data rate (DDR) memory interface, a quad-data rate (QDR) memory interface, a clock skew compensation circuit, a frequency multiplication circuit and a frequency division circuit.

3. The system of claim 1 wherein the first clock output signal from the first DLL lags the second clock output signal from the second DLL by the start offset.

4. The system of claim 1 wherein the first clock output signal from the first DLL leads the second clock output signal from the second DLL by the start offset.

5. The system of claim 1 wherein the test dataset includes a first sample taken from the second clock output signal of the second DLL during a positive edge from the first clock output signal of the first DLL and a second sample taken from the second clock output signal of the second DLL during a negative edge from the first clock output signal of the first DLL.

6. The test controller of claim 1 further comprising logic that selects a pair of DLLs from two or more DLLs in the circuitry, wherein one DLL from the selected pair is the first DLL and another DLL from the selected pair is the second DLL.

7. A built-in self-test method for two or more delay locked loop (DLLs) comprising the steps of:

providing a clock input signal to a first DLL and the clock input signal to a second DLL, wherein the clock input signal delayed by the first DLL corresponds to a first clock output signal and the clock input signal delayed by the second DLL corresponds to a second clock output signal;

initializing the first DLL with a first delay amount causing the first clock output signal from the first DLL to become offset from the second clock output signal of the second DLL by a start offset;

modifying both the first delay amount provided to the first DLL and a second delay amount provided to the second DLL by a common delay amount selected from a set of common delay amounts;

determining if modifying both the first delay amount to the first DLL and the second delay amount to the second DLL by the common delay amount causes a change in the offset between the second clock output signal and the first clock output signal set to the start offset in the initializing step; and

indicating the first DLL may not be functioning properly when the determining step indicates that the start offset set initially between the first clock output signal and the second clock output signal has changed in response to modifying both the first delay amount and the second delay amount by the common delay amount.

8. The method of claim 7 wherein the circuitry having two or more DLLs is selected from a set of circuits including:

a double-data rate (DDR) memory interface, a quad-data rate (QDR) memory interface, a clock skew compensation circuit, a frequency multiplication circuit and a frequency division circuit.

9. The method of claim 7 wherein initializing the first DLL with the first delay amount causes the first clock output signal from the first DLL to lead the second clock output signal from the second DLL by the start offset.

10. The method of claim 7 wherein initializing the first DLL with the first delay input causes the first clock output signal from the first DLL to lag the second clock output signal from the second DLL by the start offset.

11. The method of claim 7 wherein the determining step further comprises the steps of:

receiving a comparison dataset with values expected from the second clock output signal when the first DLL is operating properly;

creating a test dataset by sampling values from the second clock output signal of the second DLL on at least one edge of the first clock output signal of the first DLL; and

comparing the comparison dataset with the test dataset as an indication of the offset between the first clock output signal and the second clock output signal.

12. The method of claim 11 wherein creating the test dataset further comprises:

generating a first sample of the second clock output signal from the second DLL when there is a positive edge from the first clock output signal of the first DLL; and

generating a second sample of the second clock output signal from the second DLL when there is a negative edge from the first clock output signal of the first DLL.

13. The method of claim 11 wherein the offset is approximately the same as the start offset when the step of comparing results in the comparison dataset matching the test dataset.

14. The method of claim 11 wherein the offset is not approximately the same as the start offset when the step of comparing results in the comparison dataset not matching the test dataset.

15. A computer program product for operating a built-in self-test for two or more delay locked loop (DLLs), tangibly stored on a computer readable medium, comprising instructions operable to cause a programmable processor to:

provide a clock input signal to a first DLL and to a second DLL, wherein the clock input signal delayed by the first DLL corresponds to a first clock output signal and the clock input signal delayed by the second DLL corresponds to a second clock output signal;

initialize the first DLL by a first delay amount that causes the first clock output signal of the first DLL to be offset from the second clock output signal of the second DLL by a start offset;

modify both the first delay amount provided to the first DLL and a second delay amount provided to the second DLL by a common delay amount selected from a set of common delay amounts;

determine if modifying both the first delay amount to the first DLL and the second delay amount to the second DLL by the common delay amount causes a change in the offset between the second clock output signal and the first clock output signal set initially to the start offset; and

indicate that the first DLL may not be functioning properly when the offset between the second clock output signal and the first clock output has changed from the start offset in response to a modification of both the first delay amount and the second delay amount by the common delay amount.

16. The computer program product of claim 15 wherein the circuitry having two or more DLLs is selected from a set of circuits including:

a double-data rate (DDR) memory interface, a quad-data rate (QDR) memory interface, a clock skew compensation circuit, a frequency multiplication circuit and a frequency division circuit.

17. The computer program product of claim 15 wherein the change to the first delay amount causes the first clock output signal from the first DLL to lead the second clock output signal from the second DLL by the start offset.

18. The computer program product of claim 15 wherein the change to the first delay amount causes the first clock output signal from the first DLL to lag the second clock output signal from the second DLL by the start offset.

19. The computer program product of claim 15 wherein the instructions that determine the change in the offset further comprises instructions operable to cause the programmable processor to:

receive a comparison dataset with values expected from the second clock output signal when the first DLL is operating properly;

create a test dataset by measuring values from the second clock output signal on at least one edge of the first clock output signal; and

compare the comparison dataset with the test dataset as an indication of the offset between the first clock output signal and the second clock output signal.

20. The computer program product of claim 19 wherein the start offset has not changed when the comparison results in the comparison dataset match the test dataset.

21. The computer program product of claim 19 wherein the start offset has changed when the comparison results in the comparison dataset do not match the test dataset.

22. The computer program product of claim 19 wherein the instructions that create a test dataset by measuring values from the second clock output signal on at least one edge of the first clock output signal further comprises instructions operable to cause the programmable processor to:

generate a first sample of the second clock output signal from the second DLL when there is a positive edge from the first clock output signal of the first DLL; and

generate a second sample of the second clock output signal from the second DLL when there is a negative edge from the first clock output signal of the first DLL.