Pulse generation circuit and semiconductor device
First Claim
Patent Images
1. A gate driver comprising a plurality of unit circuits each comprising:
- a first transistor;
a second transistor;
a plurality of third transistors;
a plurality of fourth transistors;
a plurality of fifth transistors;
a sixth transistor; and
a seventh transistor,wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,wherein one of a source and a drain of one of the plurality of third transistors is electrically connected to one of a source and a drain of one of the plurality of fourth transistors,wherein one of a source and a drain of one of the plurality of fifth transistors is electrically connected to a gate of the one of the plurality of third transistors,wherein the one of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of each of the plurality of fifth transistors,wherein a gate of the second transistor is electrically connected to gates of the plurality of fourth transistors,wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor,wherein the one of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor,wherein a first power supply voltage is supplied to the other of the source and the drain of the first transistor, gates of the plurality of fifth transistors, and the other of the source and the drain of the sixth transistor,wherein a second power supply voltage is supplied to the other of the source and the drain of the second transistor, the other of the source and the drain of each of the plurality of fourth transistors, and the other of the source and the drain of the seventh transistor,wherein a set signal from the previous unit circuit is input to a gate of the first transistor and a gate of the seventh transistor, andwherein a reset signal from the next unit circuit is input to a gate of the sixth transistor.
0 Assignments
0 Petitions
Accused Products
Abstract
Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every M rows. The shift register includes k first unit circuits connected in cascade. The demultiplexer includes k second unit circuits to each of which a signal is input from the first unit circuit and to each of which M gate lines are connected. The second unit circuit selects one or more wirings which output an input signal from the first unit circuit among M gate lines, and outputs the signal from the first unit circuit to the selected wiring(s). Since gate signals can be output from an output of a one-stage shift register to the M gate lines, the width of the shift register can be narrowed.
52 Citations
2 Claims
-
1. A gate driver comprising a plurality of unit circuits each comprising:
-
a first transistor; a second transistor; a plurality of third transistors; a plurality of fourth transistors; a plurality of fifth transistors; a sixth transistor; and a seventh transistor, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein one of a source and a drain of one of the plurality of third transistors is electrically connected to one of a source and a drain of one of the plurality of fourth transistors, wherein one of a source and a drain of one of the plurality of fifth transistors is electrically connected to a gate of the one of the plurality of third transistors, wherein the one of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of each of the plurality of fifth transistors, wherein a gate of the second transistor is electrically connected to gates of the plurality of fourth transistors, wherein one of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor, wherein the one of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor, wherein a first power supply voltage is supplied to the other of the source and the drain of the first transistor, gates of the plurality of fifth transistors, and the other of the source and the drain of the sixth transistor, wherein a second power supply voltage is supplied to the other of the source and the drain of the second transistor, the other of the source and the drain of each of the plurality of fourth transistors, and the other of the source and the drain of the seventh transistor, wherein a set signal from the previous unit circuit is input to a gate of the first transistor and a gate of the seventh transistor, and wherein a reset signal from the next unit circuit is input to a gate of the sixth transistor.
-
-
2. A gate driver comprising:
-
first to eleventh transistors, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the sixth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the seventh transistor, wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the eighth transistor, wherein one of a source and a drain of the ninth transistor is electrically connected to a gate of the third transistor, wherein one of a source and a drain of the tenth transistor is electrically connected to a gate of the fourth transistor, wherein one of a source and a drain of the eleventh transistor is electrically connected to a gate of the fifth transistor, wherein the one of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the ninth transistor, the other of the source and the drain of the tenth transistor, and the other of the source and the drain of the eleventh transistor, wherein a gate of the second transistor is electrically connected to a gate of the sixth transistor, a gate of the seventh transistor, and a gate of the eighth transistor, wherein a first clock signal is input to the other of the source and the drain of the third transistor, wherein a second clock signal is input to the other of the source and the drain of the fourth transistor, and wherein a third clock signal is input to the other of the source and the drain of the fifth transistor.
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
-
Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
-
InventorsMiyake, Hiroyuki, Toyotaka, Kouhei
-
Primary Examiner(s)SKIBINSKI, THOMAS S
-
Application NumberUS15/300,000Publication NumberTime in Patent Office578 DaysField of Search327295-297, 327241, 327242, 327427, 327434, 327437, 327408, 327165, 327166, 327170-177, 327184, 377 64, 377 68, 377 78, 377 79, 377 54, 326 46, 345 42US Class CurrentCPC Class CodesG09G 2300/0404 Matrix technologiesG09G 2300/0413 Details of dummy pixels or ...G09G 2310/0205 Simultaneous scanning of se...G09G 2310/0286 Details of a shift register...G09G 2310/0291 Details of output amplifier...G09G 3/3266 Details of drivers for scan...G09G 3/3648 using an active matrix G09G...G09G 3/3677 suitable for active matrice...G09G 3/3696 Generation of voltages supp...G09G 5/18 Timing circuits for raster ...G11C 19/28 using semiconductor element...H03K 3/356026 with synchronous operation ...
