Memory devices providing a refresh request and memory controllers responsive to a refresh request
First Claim
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1. A memory device, comprising:
- a memory cell array including a plurality of rows of memory cells;
a refresh request circuit configured to issue requests for refresh operations to an external device; and
control logic configured to receive commands from the external device and control the memory device in accordance with the received commands,wherein the refresh request circuit is configured to issue a request for a refresh operation for a first row of memory cells of the plurality of rows of memory cells to the external device, the request for the refresh operation issued to the external device in conjunction with an address of the first row of memory cells, and the control logic is configured to receive a first refresh command to refresh the first row from the external device and cause a refresh operation of the first row of memory cells in response to the first refresh command, andwherein the refresh request circuit is configured to issue each request for a refresh operation as a refresh request signal via a first terminal of the memory device.
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Abstract
A memory system includes at least one memory device and a memory controller. The at least one memory device includes a refresh request circuit that generates refresh request signals at timings based on data retention times of memory cells, such as based on individual data retention times of a memory cell row. The memory controller schedules operation commands for the at least one memory device in response to the received refresh request signals.
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Citations
26 Claims
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1. A memory device, comprising:
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a memory cell array including a plurality of rows of memory cells; a refresh request circuit configured to issue requests for refresh operations to an external device; and control logic configured to receive commands from the external device and control the memory device in accordance with the received commands, wherein the refresh request circuit is configured to issue a request for a refresh operation for a first row of memory cells of the plurality of rows of memory cells to the external device, the request for the refresh operation issued to the external device in conjunction with an address of the first row of memory cells, and the control logic is configured to receive a first refresh command to refresh the first row from the external device and cause a refresh operation of the first row of memory cells in response to the first refresh command, and wherein the refresh request circuit is configured to issue each request for a refresh operation as a refresh request signal via a first terminal of the memory device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 16, 19, 20, 21, 22, 23, 24, 25)
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11. A memory controller comprising:
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a command generator configured to generate memory commands in response to externally received command requests from a host; a scheduler configured to generate a command queue providing a sequential list of memory commands to be issued to a memory device external to the memory controller, the sequential list of memory commands comprising the memory commands generated by the command generator in response to the command requests from the host; at least one terminal to receive a refresh request from the memory device; and a storage unit configured to store one or more addresses of the memory device received with the refresh request from the memory device, wherein the scheduler is configured to alter the sequential list of memory commands in the command queue to insert refresh commands into the command queue, the refresh commands including the one or more addresses of the memory device stored in the storage unit to identify locations of the memory device to be refreshed. - View Dependent Claims (12, 13, 14, 15, 17, 18)
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26. A memory device, comprising:
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a memory cell array including a plurality of rows of memory cells including a first row of memory cells and a second row of memory cells; a refresh request circuit configured to issue requests for refresh operations to an external device, the requests for refresh operations including a first request for a refresh operation of the first row of memory cells and a second request for a refresh operation of the second row of memory cells; and control logic configured to receive commands from the external device and control the memory device in accordance with the received commands, wherein the refresh request circuit is configured to issue the first request for the refresh operation of the first row of memory cells to the external device in conjunction with transmitting an address of the first row of memory cells to the external device, and the control logic is configured to receive a first refresh command to refresh the first row from the external device and cause a refresh operation of the first row of memory cells in response to the first refresh command, wherein the refresh request circuit is configured to issue the second request for the refresh operation of the second row of memory cells to the external device in conjunction with transmitting an address of the second row of memory cells to the external device, and the control logic is configured to receive a second refresh command to refresh the second row from the external device and cause a refresh operation of the second row of memory cells in response to the second refresh command, and wherein a duration between the first request for the first refresh operation and the second request for the second refresh operation is responsive to at least one of a look-up table of the memory device and a counter of the memory device.
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Specification