Line memory device and image sensor including the same

• US 9,978,431 B2
• Filed: 08/06/2015
• Issued: 05/22/2018
• Est. Priority Date: 03/05/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jung, Wun-Ki, Kwon, Min-Ho, Yoo, Kwi-Sung, Choi, Won-Ho, Lee, Dong-Hun, Ham, Seog-Heon
• Primary Examiner(s): Lee, John
• Application Number:
  US14/819,978
• Publication Number:
  US 20150340070A1
• Time in Patent Office: 1,020 Days
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1033 using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H01L 27/146 Imager structures
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers

Abstract

A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.

Claims

1. A line memory device, comprising:

a plurality of memory cells each configured to store a respective different memory data bit from among memory data bits;

a sense amplifier;

a data line pair coupled to the memory cells and to the sense amplifier to sequentially transfer the memory data bits from the memory cells to the sense amplifier, wherein each of the plurality of memory cells is disposed a corresponding different distance from the sense amplifier along the data line pair such that the memory data bits are transferred from the memory cells to the sense amplifier with delays that are different from each other, and wherein a first one of the memory cells is a farthest distance among the memory cells from the sense amplifier along the data line pair and stores a first data bit from among the memory data bits which is transferred to the sense amplifier with a longest delay among the delays; and

an output unit configured to sample an output of the sense amplifier for each of the memory data bits in response to a read clock signal so as to sequentially output retimed data bits each corresponding to a respective different one of the memory data bits,

wherein the read clock signal has a cyclic period which is less than the longest delay.

2. The line memory device of claim 1, wherein the memory data bits are sequentially transferred to the sense amplifier in order beginning from the first one of the memory cells and ending with a last one of the memory cells, wherein the last one of the memory cells is a shortest distance among the memory cells from the sense amplifier along the data line pair.

3. The line memory device of claim 1, wherein the memory data bits are sequentially transferred to the sense amplifier in order beginning from a last one of the memory cells and ending with the first one of the memory cells, wherein the last one of the memory cells is a shortest distance among the memory cells from the sense amplifier along the data line pair.

4. The line memory device of claim 1, wherein the output unit is configured to sample the output of the sense amplifier in response to a first edge of the read clock signal to output first bits of the retimed data bits, and to sample the output of the sense amplifier in response to a second edge of the read clock signal to output second bits of the retimed data bits, the first edge corresponding to one of a rising edge and a falling edge, and the second edge corresponding to an other of the rising edge and the falling edge.

5. The line memory device of claim 4, wherein the first bits of the retimed data bits correspond to the memory data bits of first and third groups of the memory cells, and the second bits of the retimed data bits correspond to the memory data bits of a second group of the memory cells, the first group of the memory cells disposed farthest away from the sense amplifier among the plurality of memory cells, the third group of the memory cells disposed closest to the sense amplifier among the plurality of memory cells, and the second group of the memory cells disposed between the first group and the third group.

6. The line memory device of claim 1, wherein the output unit comprises:

a first shift register comprising a first plurality of flip-flops cascaded in series and configured to sample the output of the sense amplifier in response to a first edge of the read clock signal, the first edge corresponding to one of a rising edge and a falling edge;

a second shift register comprising a second plurality of flip-flops cascaded in series and configured to sample the output of the sense amplifier in response to a second edge of the read clock signal, the second edge corresponding to an other of the rising edge and the falling edge;

a multiplexer configured to select one of an output of the first shift register and an output of the second shift register in response to a retiming selection signal; and

a retiming control block configured to generate the retiming selection signal based on the delays.

7. The line memory device of claim 6, wherein the retimed data bits corresponding to the memory data bits of first and third groups of the memory cells are provided from the second shift register that samples the output of the sense amplifier in response to the falling edge of the read clock signal, and the retimed data bits corresponding to the memory data bits of a second group of the memory cells are provided from the first shift register that samples the output of the sense amplifier in response to the rising edge of the read clock signal,

the first group of the memory cells disposed farthest away from the sense amplifier among the plurality of memory cells, the third group of the memory cells disposed closest to the sense amplifier among the plurality of memory cells, and the second group of the memory cells disposed between the first group and the third group.

8. The line memory device of claim 6, wherein the retiming control block comprises:

a detector configured to detect at least one retiming point based on the delays which are different from each other; and

a selection signal generator configured to generate the retiming selection signal based on the at least one retiming point.

9. The line memory device of claim 8, wherein the detector comprises:

a plurality of dummy memory cells configured to respectively store patterned data bits;

a dummy sense amplifier;

a dummy data line pair coupled to the dummy memory cells and to the dummy sense amplifier to sequentially transfer the patterned data bits from the dummy memory cells to the dummy sense amplifier, wherein each of the plurality of dummy memory cells is disposed a corresponding different distance from the dummy sense amplifier along the dummy data line pair such that the patterned data bits are transferred from the dummy memory cells to the dummy sense amplifier with corresponding dummy delays; and

a detection signal generator configured to generate a detection signal by comparing first detection data bits and second detection data bits sampled from an output of the dummy sense amplifier, the detection signal indicating the at least one retiming point, the first detection data bits sampled in response to the first edge of the read clock signal, the second detection data bits sampled in response to the second edge of the read clock signal.

10. The line memory device of claim 9, wherein a connection of the dummy data line pair to the dummy memory cells and the dummy sense amplifier is substantially the same as a connection of the data line pair to the memory cells and the sense amplifier, and the dummy delays are each substantially the same as respective ones of the delays.

11. The line memory device of claim 9, wherein the dummy memory cells comprise read only memory (ROM) cells and the patterned data bits are stored in the ROM cells.

12. The line memory device of claim 9, wherein the dummy memory cells comprise one of random access memory (RAM) cells, latches and flip-flops, and the patterned data bits are written in the dummy memory cells based on data provided from an external device.

13. An image sensor comprising:

a pixel array including a plurality of pixels configured to capture an image;

an analog-to-digital convertor block configured to convert analog signals from the pixels to digital signals; and

a line memory device configured to buffer the digital signals as memory data bits, the line memory device comprising

a plurality of memory cells each configured to store a respective different memory data bit from among the memory data bits;

a sense amplifier;

a data line pair coupled to the memory cells and to the sense amplifier to sequentially transfer the memory data bits from the memory cells to the sense amplifier, wherein each of the plurality of memory cells is disposed a corresponding different distance from the sense amplifier along the data line pair such that the memory data bits are transferred from the memory cells to the sense amplifier with delays that are different from each other, and wherein a first one of the memory cells is a farthest distance among the memory cells from the sense amplifier along the data line pair and stores a first data bit from among the memory data bits which is transferred to the sense amplifier with a longest delay among the delays; and

an output unit configured to sample an output of the sense amplifier for each of the memory data bits in response to a read clock signal so as to sequentially output retimed data bits each corresponding to a respective different one of the memory data bits,

wherein the read clock signal has a cyclic period which is less than the longest delay.

14. The image sensor of claim 13, wherein the memory data bits are sequentially transferred to the sense amplifier in order beginning from the first one of the memory cells and ending with a last one of the memory cells, wherein the last one of the memory cells is a shortest distance among the memory cells from the sense amplifier along the data line pair.

15. The image sensor of claim 13, wherein the memory data bits are sequentially transferred to the sense amplifier in order beginning from a last one of the memory cells and ending with the first one of the memory cells, wherein the last one of the memory cells is a shortest distance among the memory cells from the sense amplifier along the data line pair.

16. The image sensor of claim 13, wherein the output unit comprises:

a first shift register comprising a first plurality of flip-flops cascaded in series and configured to sample the output of the sense amplifier in response to a first edge of the read clock signal, the first edge corresponding to one of a rising edge and a falling edge;

a second shift register comprising a second plurality of flip-flops cascaded in series and configured to sample the output of the sense amplifier in response to a second edge of the read clock signal, the second edge corresponding to an other of the rising edge and the falling edge;

a multiplexer configured to select one of an output of the first shift register and an output of the second shift register in response to a retiming selection signal; and

a retiming control block configured to generate the retiming selection signal based on the delays.

17. The image sensor of claim 16, wherein the retiming control block comprises:

a detector configured to detect at least one retiming point based on the delays which are different from each other; and

a selection signal generator configured to generate the retiming selection signal based on the at least one retiming point.

18. The image sensor of claim 17, wherein the detector comprises:

a plurality of dummy memory cells configured to respectively store patterned data bits;

a dummy sense amplifier;

a dummy data line pair coupled to the dummy memory cells and to the dummy sense amplifier to sequentially transfer the patterned data bits from the dummy memory cells to the dummy sense amplifier, wherein each of the plurality of dummy memory cells is disposed a corresponding different distance from the dummy sense amplifier along the dummy data line pair such that the patterned data bits are transferred from the dummy memory cells to the dummy sense amplifier with corresponding dummy delays; and

a detection signal generator configured to generate a detection signal by comparing first detection data bits and second detection data bits sampled from an output of the dummy sense amplifier, the detection signal indicating the at least one retiming point, the first detection data bits sampled in response to the first edge of the read clock signal, the second detection data bits sampled in response to the second edge of the read clock signal.

19. A line memory device, comprising:

a plurality of memory cells each configured to store a respective different memory data bit from among memory data bits;

a sense amplifier;

a data line pair coupled to the memory cells and to the sense amplifier to sequentially transfer the memory data bits from the memory cells to the sense amplifier, wherein each of the plurality of memory cells is disposed a corresponding different distance from the sense amplifier along the data line pair such that the memory data bits are transferred from the memory cells to the sense amplifier with delays that are different from each other; and

an output unit configured to sample an output of the sense amplifier for each of the memory data bits in response to a read clock signal so as to sequentially output retimed data bits each corresponding to a respective different one of the memory data bits in response to a retiming selection signal,

wherein the output unit comprises a plurality of dummy memory cells, a dummy sense amplifier, a dummy data line pair, and a detection signal generator,

wherein the detection signal generator is configured to generate a detection signal by comparing first detection bits and second detection bits sampled from an output of the dummy sense amplifier, and the output unit is configured to generate the retiming selection signal based on the detection signal.

20. The line memory device of claim 19, wherein a connection of the dummy data line pair to the dummy memory cells and the dummy sense amplifier is substantially the same as a connection of the data line pair to the memory cells and the sense amplifier.