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Line memory device and image sensor including the same

  • US 9,978,431 B2
  • Filed: 08/06/2015
  • Issued: 05/22/2018
  • Est. Priority Date: 03/05/2012
  • Status: Active Grant
First Claim
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1. A line memory device, comprising:

  • a plurality of memory cells each configured to store a respective different memory data bit from among memory data bits;

    a sense amplifier;

    a data line pair coupled to the memory cells and to the sense amplifier to sequentially transfer the memory data bits from the memory cells to the sense amplifier, wherein each of the plurality of memory cells is disposed a corresponding different distance from the sense amplifier along the data line pair such that the memory data bits are transferred from the memory cells to the sense amplifier with delays that are different from each other, and wherein a first one of the memory cells is a farthest distance among the memory cells from the sense amplifier along the data line pair and stores a first data bit from among the memory data bits which is transferred to the sense amplifier with a longest delay among the delays; and

    an output unit configured to sample an output of the sense amplifier for each of the memory data bits in response to a read clock signal so as to sequentially output retimed data bits each corresponding to a respective different one of the memory data bits,wherein the read clock signal has a cyclic period which is less than the longest delay.

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