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Memory cells, memory cell arrays, methods of using and methods of making

  • US 9,978,450 B2
  • Filed: 11/13/2017
  • Issued: 05/22/2018
  • Est. Priority Date: 11/29/2007
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • a semiconductor memory array comprising;

    a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include;

    a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said memory cell; and

    a nonvolatile memory comprising a resistance change element configured to store data stored in said floating body upon transfer thereto;

    wherein said nonvolatile memory is configured to restore said data to said floating body; and

    a control circuit configured to perform said restore operation.

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