Memory cells, memory cell arrays, methods of using and methods of making
First Claim
1. An integrated circuit comprising:
- a semiconductor memory array comprising;
a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include;
a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said memory cell; and
a nonvolatile memory comprising a resistance change element configured to store data stored in said floating body upon transfer thereto;
wherein said nonvolatile memory is configured to restore said data to said floating body; and
a control circuit configured to perform said restore operation.
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Accused Products
Abstract
A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.
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Citations
20 Claims
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1. An integrated circuit comprising:
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a semiconductor memory array comprising; a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include; a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to said memory cell; and a nonvolatile memory comprising a resistance change element configured to store data stored in said floating body upon transfer thereto; wherein said nonvolatile memory is configured to restore said data to said floating body; and a control circuit configured to perform said restore operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit comprising:
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a semiconductor memory array comprising; a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include; a silicon controlled rectifier device configured to store data when power is applied to said memory cell; and a nonvolatile memory comprising a resistance change element configured to store data stored in said silicon controlled rectifier device upon transfer thereto; wherein said nonvolatile memory is configured to restore said data to said silicon controlled rectifier device; and a control circuit configured to perform said restore operation. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification