Method for writing in an EEPROM memory and corresponding device

• US 9,978,452 B2
• Filed: 08/21/2017
• Issued: 05/22/2018
• Est. Priority Date: 02/22/2016
• Status: Active Grant

• Current Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Inventors: Tailliet, Franois
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US15/682,102
• Publication Number:
  US 20170345502A1
• Time in Patent Office: 274 Days
• Field of Search: 36518518
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region

Abstract

A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.

Claims

1. A method, comprising:

applying an erase voltage to a first control gate in a first erasing phase, a first transistor comprising the first control gate, a first floating gate underlying the first control gate, and a first gate dielectric underlying the first floating gate;

applying the erase voltage to a second control gate in the first erasing phase, a second transistor comprising the second control gate, a second floating gate underlying the second control gate, and a second gate dielectric underlying the second floating gate, wherein the second floating gate is coupled to the first floating gate to form a common floating gate;

applying a zero voltage to a drain of the first transistor and a drain of the second transistor in the first erasing phase;

maintaining the first control gate and the second control gate at the erase voltage in a second erasing phase;

maintaining the drain of the first transistor at the zero voltage in the second erasing phase; and

applying a first auxiliary voltage to the drain of the second transistor in the second erasing phase.

2. The method of claim 1, wherein applying the erase voltage to the first control gate in the first erasing phase and applying the erase voltage to the second control gate in the first erasing phase comprise simultaneously applying the erase voltage to the first control gate and the second control gate in the first erasing phase.

3. The method of claim 1, wherein the erase voltage comprises a non-zero voltage.

4. The method of claim 1, wherein applying the erase voltage to the first control gate in the first erasing phase and applying the erase voltage to the second control gate in the first erasing phase comprise linearly changing a voltage at the first control gate and at the second control gate from an initial voltage to the erase voltage.

5. The method of claim 4, wherein the initial voltage comprises the zero voltage.

6. The method of claim 1, wherein the first auxiliary voltage is equal to the erase voltage.

7. The method of claim 1, wherein applying the first auxiliary voltage to the drain of the second transistor in the second erasing phase comprises linearly changing a voltage at the drain of the second transistor from the zero voltage to the first auxiliary voltage.

8. The method of claim 1, further comprising:

applying the zero voltage to the first control gate and the second control gate in a first writing phase;

applying a program voltage to the drain of the first transistor and the drain of the second transistor in the first writing phase;

maintaining the first control gate and the second control gate at the zero voltage in a second writing phase;

maintaining the drain of the first transistor at the program voltage in the second writing phase; and

applying a second auxiliary voltage to the drain of the second transistor in the second writing phase.

9. The method of claim 8, wherein the second auxiliary voltage comprises a non-zero voltage.

10. The method of claim 8, wherein the second auxiliary voltage is less than the program voltage.

11. The method of claim 8, wherein the program voltage is equal to the erase voltage.

12. The method of claim 8, wherein applying the second auxiliary voltage to the drain of the second transistor in the second writing phase comprises linearly changing a voltage at the drain of the second transistor from the program voltage to the second auxiliary voltage.

13. The method of claim 8, wherein applying the program voltage to the drain of the first transistor and the drain of the second transistor in the first writing phase comprises linearly changing a voltage at the drain of the first transistor and the drain of the second transistor from the zero voltage to the program voltage.

14. A memory device, comprising:

a memory location comprising;

a first transistor comprising a first control gate, a first floating gate underlying the first control gate, and a first gate dielectric underlying the first floating gate;

a second transistor comprising a second control gate, a second floating gate underlying the second control gate, and a second gate dielectric underlying the second floating gate, wherein the second floating gate is coupled to the first floating gate to form a common floating gate;

a processor; and

a computer-readable storage medium storing a program to be executed by the processor, the program including instructions for;

applying an erase voltage to the first control gate and the second control gate in a first erasing phase;

applying a zero voltage to a drain of the first transistor and a drain of the second transistor in the first erasing phase;

maintaining the first control gate and the second control gate at the erase voltage in a second erasing phase;

maintaining the drain of the first transistor at the zero voltage in the second erasing phase; and

applying a first auxiliary voltage to the drain of the second transistor in the second erasing phase.

15. The memory device of claim 14, further comprising:

a first access transistor coupled in series with the first transistor and controllable by a voltage on a word line; and

a second access transistor coupled in series with the second transistor and controllable by the voltage on the word line.

16. The memory device of claim 14, wherein the program further includes instructions for:

applying the zero voltage to the first control gate and the second control gate in a first writing phase;

applying a program voltage to the drain of the first transistor and the drain of the second transistor in the first writing phase;

maintaining the first control gate and the second control gate at the zero voltage in a second writing phase;

maintaining the drain of the first transistor at the program voltage in the second writing phase; and

applying a second auxiliary voltage to the drain of the second transistor in the second writing phase.

17. A method for writing a first memory cell of a memory location of an electrically-erasable and programmable memory type, wherein the first memory cell comprises a first transistor having a first control gate, a first floating gate underlying the first control gate, and a first gate dielectric underlying the first floating gate, the memory location further comprising a second memory cell comprising a second transistor having a second control gate, a second floating gate underlying the second control gate, and a second gate dielectric underlying the second floating gate, wherein the second floating gate is coupled to the first floating gate to form a common floating gate, the method comprising:

applying an erase voltage to the first control gate and to the second control gate and applying a zero voltage to a drain of the first transistor and a drain of the second transistor in a first writing phase, wherein an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric in the first writing phase; and

maintaining the zero voltage on the drain of second transistor and applying an auxiliary voltage to the drain of the first transistor in a second writing phase, the auxiliary voltage having a value chosen so as to increase a potential of the first floating gate of the first transistor, and wherein a voltage across the first gate dielectric but not the second gate dielectric is increased in the second writing phase.

18. The method of claim 17, wherein applying the erase voltage to the first control gate and to the second control gate comprises linearly increasing a voltage at the first control gate and the second control gate to the erase voltage.

19. The method of claim 17, wherein the auxiliary voltage is equal to the erase voltage.

20. The method of claim 17, wherein the erase voltage is between 10 volts and 20 volts.