Techniques for reducing read disturb in partially written blocks of non-volatile memory
First Claim
Patent Images
1. A method, comprising:
- performing a first sense operation on a particular word line of a block comprising a plurality of word lines having a sequential program ordering, wherein the first sense operation indicates that memory cells coupled to the particular word line are programmed, and comprises;
applying a first non-selected word line voltage to word lines between the particular word line and a first end of the block, the first non-selected word line voltage configured to cause programmed memory cells to conduct, andapplying a second non-selected word line voltage to word lines between the particular word line and a second end of the block, the second non-selected word line voltage configured to cause erased memory cells to conduct, wherein the second non-selected word line voltage is less than the first non-selected word line voltage;
selecting a subsequent word line for a second sense operation in response to the first sense operation indicating that memory cells coupled to the particular word line are programmed, the subsequent word line selected to follow the particular word line in the sequential program ordering; and
determining that the particular word line is a last word line programmed in the sequential program ordering in response to the second sense operation indicating that memory cells coupled to the subsequent word line.
2 Assignments
0 Petitions
Accused Products
Abstract
Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.
-
Citations
28 Claims
-
1. A method, comprising:
-
performing a first sense operation on a particular word line of a block comprising a plurality of word lines having a sequential program ordering, wherein the first sense operation indicates that memory cells coupled to the particular word line are programmed, and comprises; applying a first non-selected word line voltage to word lines between the particular word line and a first end of the block, the first non-selected word line voltage configured to cause programmed memory cells to conduct, and applying a second non-selected word line voltage to word lines between the particular word line and a second end of the block, the second non-selected word line voltage configured to cause erased memory cells to conduct, wherein the second non-selected word line voltage is less than the first non-selected word line voltage; selecting a subsequent word line for a second sense operation in response to the first sense operation indicating that memory cells coupled to the particular word line are programmed, the subsequent word line selected to follow the particular word line in the sequential program ordering; and determining that the particular word line is a last word line programmed in the sequential program ordering in response to the second sense operation indicating that memory cells coupled to the subsequent word line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A memory device, comprising:
sense circuitry coupled to an array of memory cells, each memory cell coupled to one of a plurality of bit lines and one of a plurality of word lines, the sense circuitry configured for identifying a first erased word line in a sequential programming order for the word lines from a source end of the array to a drain end of the array by; sensing that memory cells coupled to a designated one of the word lines are programmed while word lines between the designated word line and the drain end of the array are set to a low non-select voltage level and word lines between the designated word line and the source end of the array are set to a high non-select voltage level, wherein the high non-select voltage level is configured to cause erased memory cells of the array and programmed memory cells of the array to conduct, and wherein the low non-select voltage level is configured to cause the erased memory cells of the array to conduct and programmed memory cells of the array to be substantially non-conducting; selecting a word line that follows the designated word line in the sequential programming order for the word lines in response to sensing that memory cells coupled to the designated word line are programmed; and determining that the selected word line corresponds to the first erased word line in the sequential programming order for the word lines in response to sensing that memory cells coupled to the selected word line are erased while word lines between the selected word line and the drain end of the array are set to the low non-select voltage level and word lines between the selected word line and the source end of the array are set to the high non-select voltage level. - View Dependent Claims (12, 13, 14, 24)
-
15. A memory system, comprising:
-
a series of memory cells; and a controller configured to identify a first erased memory cell in the series of memory cells by performing a plurality of sense operations, wherein each sense operation is performed on a selected memory cell of the series to determine whether the selected memory cell of the series is erased, and comprises; applying a first voltage potential to control gates of one or more memory cells of the series ordered before the selected memory cell in the series, the first voltage potential configured to cause programmed memory cells of the series to be conductive during the sense operation, and applying a second voltage potential to a control gate of the selected memory cell of the series, wherein the second voltage potential is lower than the first voltage potential and is configured to cause erased memory cells of the series to be conductive during the sense operation and to cause the programmed memory cells of the series to be substantially non-conductive during the sense operation, wherein the controller determines that a particular memory cell is the first erased memory cell in the series in response to; performing a first sense operation of the plurality of sense operations on a first memory cell of the series; selecting the particular memory cell for a second sense operation of the plurality of sense operations in response to the first sense operation indicating that the first memory cell is programmed, wherein the particular memory cell is selected to follow the first memory cell in the series of memory cells; and determining that the particular memory cell is the first erased memory cell in the series in response to the second sense operation of the plurality of sense operations indicating that the particular memory cell is erased. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23)
-
-
25. An apparatus, comprising:
memory logic configured to identify a first erased word line of a memory block comprising a plurality of word lines corresponding to a program order, the memory logic configured to implement a plurality of read iterations on the memory block at respective word line offsets within the program order, wherein performing a read iteration at a current word line offset comprises; sensing bit lines of the memory block by use of sense circuitry to determine a count of bit lines that are non-conducting while word lines preceding the current word line offset are set to a high read voltage potential, and word lines following the current word line offset are set to a partial read voltage potential, wherein the high read voltage potential is configured to cause memory cells of the bit lines to conduct, and wherein the partial read voltage potential is configured to cause memory cells of the bit lines that are in an erased state to conduct and to cause memory cells of the bit lines that are in one or more of a plurality of programmed states to be substantially non-conducting; continuing the plurality of read iterations after the current read iteration in response to the determined count being greater than zero, the continuing comprising determining a next word line offset for a next read iteration of the plurality of read iterations by incrementing the current word line offset in the program order; and terminating the plurality of read iterations in response to the determined count being equal to zero, the terminating comprising determining that the current word line offset corresponds to the first erased word line of the memory block based on a read iteration preceding the current read iteration in the plurality of read iterations. - View Dependent Claims (26, 27)
-
28. A system, comprising:
-
means for performing a first sense operation on a particular word line of a block comprising a plurality of word lines having a sequential program ordering, wherein the first sense operation indicates that memory cells coupled to the particular word line are programmed, and comprises; applying a first non-selected word line voltage to word lines between the particular word line and a first end of the block, the first non-selected word line voltage configured to cause programmed memory cells to conduct, and applying a second non-selected word line voltage to word lines between the particular word line and a second end of the block, the second non-selected word line voltage configured to cause erased memory cells to conduct, wherein the second non-selected word line voltage is less than the first non-selected word line voltage; means for selecting a subsequent word line for a second sense operation in response to the first sense operation indicating that memory cells coupled to the particular word line are programmed, the subsequent word line selected to follow the particular word line in the sequential program ordering; and means for determining that the particular word line is a last word line programmed in the sequential program ordering in response to the second sense operation indicating that memory cells coupled to the subsequent word line are erased.
-
Specification