Techniques for reducing read disturb in partially written blocks of non-volatile memory

• US 9,978,456 B2
• Filed: 11/17/2014
• Issued: 05/22/2018
• Est. Priority Date: 11/17/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Khandelwal, Anubhav, Lee, Dana, Manohar, Abhijeet, Chin, Henry, Dusija, Gautam, Tuers, Daniel, Avila, Chris, Hsu, Cynthia
• Primary Examiner(s): Hur, J. H.
• Application Number:
  US14/543,660
• Publication Number:
  US 20160141046A1
• Time in Patent Office: 1,282 Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.

Claims

1. A method, comprising:

performing a first sense operation on a particular word line of a block comprising a plurality of word lines having a sequential program ordering, wherein the first sense operation indicates that memory cells coupled to the particular word line are programmed, and comprises;

applying a first non-selected word line voltage to word lines between the particular word line and a first end of the block, the first non-selected word line voltage configured to cause programmed memory cells to conduct, and

applying a second non-selected word line voltage to word lines between the particular word line and a second end of the block, the second non-selected word line voltage configured to cause erased memory cells to conduct, wherein the second non-selected word line voltage is less than the first non-selected word line voltage;

selecting a subsequent word line for a second sense operation in response to the first sense operation indicating that memory cells coupled to the particular word line are programmed, the subsequent word line selected to follow the particular word line in the sequential program ordering; and

determining that the particular word line is a last word line programmed in the sequential program ordering in response to the second sense operation indicating that memory cells coupled to the subsequent word line.

2. The method of claim 1, wherein the second sense operation comprises:

applying the first non-selected voltage to word lines that precede the subsequent word line in the sequential program ordering, and

applying the second non-selected voltage to the subsequent word line and to word lines ordered after the subsequent word line in the sequential program ordering.

3. The method of claim 1,

wherein memory cells of the block are arranged within respective memory strings, and wherein the first sense operation comprises determining that memory cells coupled to the particular word line are programmed in response to determining that sense current is substantially blocked on one or more of the memory strings during the first sense operation.

4. The method of claim 1, wherein memory cells of the block are connected to one or more bit lines, and wherein the second sense operation comprises:

determining that the memory cells coupled to the subsequent word line of the block are erased in response to sensing a current on one or more of the bit lines.

5. The method of claim 1, further comprising:

performing an initial sense operation on an initial word line of the block; and

skipping one or more word lines to select the particular word line for the first sense operation in response to determining that memory cells coupled to the initial word line are programmed, wherein a number of word lines skipped in selecting the particular word line for the first sense operation is based on a number of memory cells associated with the initial word line determined to be conducting in the initial sense operation.

6. The method of claim 5, further comprising:

skipping a first number of word lines when the number of memory cells determined to be conducting is greater than a first value, and

skipping a second number of word lines when the number of memory cells determined to be conducting is less than or equal to the first value, the second number being less than the first number.

7. The method of claim 1, wherein memory cells of the block are arranged within respective memory strings, and wherein the first non-selected word line voltage is configured to cause memory cells in any of a plurality of programmed states to conduct, the method further comprising:

performing an initial sense operation, comprising determining a number of the memory strings that are conductive when the first non-selected word line voltage is applied to word lines between an initial word line and the first end of the block and a third non-selected word line voltage is applied to word lines between the initial word line and the second end of the block, the third non-selected word line voltage configured to cause memory cells in one of an erased state and one or more of the programmed states to conduct and to cause memory cells in programmed states other than the one or more programmed memory states to be substantially non-conducting; and

selecting the particular word line for the first sense operation on the block based on the determined number.

8. The method of claim 1, wherein a plurality of the memory cells of the block are connected in a NAND string, each memory cell in the NAND string having a control gate coupled to a respective word line of the block, wherein the second sense operation comprises:

applying the first non-selected word line voltage to a set of the word lines of the block, the set including word lines between the subsequent word line and the first end of the block; and

determining that the subsequent word line is coupled to an erased memory cell in response to sensing a current on the NAND string after a settling time for the second sense operation, wherein the settling time for the second sense operation is shorter than a settling time for a sense operation that comprises applying the first non-selected word line voltage to more word lines than a number of word lines included in the set.

9. The method of claim 1, wherein the memory cells of the block are formed within one or more of a two-dimensional array and a monolithic three-dimensional semiconductor memory device with the memory cells being arranged in multiple physical levels above a silicon substrate.

10. The method of claim 1, wherein two or more of the memory cells of the block are connected in series, the two or more memory cells including a memory cell coupled to the particular word line and a memory cell coupled to the subsequent word line,

wherein the first sense operation comprises:

applying the second non-selected word line voltage to the particular word line during a first sense period,

applying a sense voltage potential to the two or more memory cells during the first sense period, and

determining that memory cells coupled to the particular word line are programmed based on current sensed through the two or more memory cells during the first sense period, and

wherein the second sense operation comprises;

applying the second non-selected word line voltage to the subsequent word line during a second sense period,

applying the first non-selected word line voltage to the particular word line during the second sense period,

applying the sense voltage potential to the two or more memory cells during the second sense period, and

determining that memory cells coupled to the subsequent word line are erased based on current sensed through the two or more memory cells during the second sense period.

11. A memory device, comprising:

sense circuitry coupled to an array of memory cells, each memory cell coupled to one of a plurality of bit lines and one of a plurality of word lines, the sense circuitry configured for identifying a first erased word line in a sequential programming order for the word lines from a source end of the array to a drain end of the array by;

sensing that memory cells coupled to a designated one of the word lines are programmed while word lines between the designated word line and the drain end of the array are set to a low non-select voltage level and word lines between the designated word line and the source end of the array are set to a high non-select voltage level, wherein the high non-select voltage level is configured to cause erased memory cells of the array and programmed memory cells of the array to conduct, and wherein the low non-select voltage level is configured to cause the erased memory cells of the array to conduct and programmed memory cells of the array to be substantially non-conducting;

selecting a word line that follows the designated word line in the sequential programming order for the word lines in response to sensing that memory cells coupled to the designated word line are programmed; and

determining that the selected word line corresponds to the first erased word line in the sequential programming order for the word lines in response to sensing that memory cells coupled to the selected word line are erased while word lines between the selected word line and the drain end of the array are set to the low non-select voltage level and word lines between the selected word line and the source end of the array are set to the high non-select voltage level.

12. The memory device of claim 11, wherein:

the memory cells comprise non-volatile memory cells, and

the array of memory cells comprises one or more of a two-dimensional array and a three-dimensional array.

13. The memory device of claim 11, wherein:

the memory cells comprise multi-state memory cells capable of being in one of an erased state and one of a plurality of programmed states,

the low non-select voltage level is configured to cause memory cells in the erased state to conduct and to cause such that memory cells programmed to any one of the plurality of programmed states to be substantially non-conducting, and

the high non-select voltage level is configured to cause memory cells in any of the erased state and the plurality of programmed states to conduct.

14. The memory device of claim 11, wherein the sense circuitry is configured to determine that the memory cells coupled to the selected word line are erased in response to sensing a voltage on one or more of the bit lines during a first sense time, and wherein the first sense time is less than a read sense time associated with a read operation on the array of memory cells.

24. The memory device of claim 11, wherein the sense circuitry is further configured to perform a plurality of read operations on bit lines of the array, wherein an initial one of the read operations comprises:

sensing bit lines of the array while word lines from a starting point within the word lines to a source end of the array are set to a first partial non-select voltage level, wherein the first partial non-select voltage level is between the low non-select voltage level and the high non-select voltage level, and is configured to cause memory cells in one of an erased state and first programmed state to conduct and to cause memory cells in one or more second programmed states to be substantially non-conducting; and

advancing the starting point for a next read operation by a determined amount of word lines, the determined amount corresponding to a number of bit lines sensed as being conductive in the initial read operation.

15. A memory system, comprising:

a series of memory cells; and

a controller configured to identify a first erased memory cell in the series of memory cells by performing a plurality of sense operations, wherein each sense operation is performed on a selected memory cell of the series to determine whether the selected memory cell of the series is erased, and comprises;

applying a first voltage potential to control gates of one or more memory cells of the series ordered before the selected memory cell in the series, the first voltage potential configured to cause programmed memory cells of the series to be conductive during the sense operation, and

applying a second voltage potential to a control gate of the selected memory cell of the series, wherein the second voltage potential is lower than the first voltage potential and is configured to cause erased memory cells of the series to be conductive during the sense operation and to cause the programmed memory cells of the series to be substantially non-conductive during the sense operation,

wherein the controller determines that a particular memory cell is the first erased memory cell in the series in response to;

performing a first sense operation of the plurality of sense operations on a first memory cell of the series;

selecting the particular memory cell for a second sense operation of the plurality of sense operations in response to the first sense operation indicating that the first memory cell is programmed, wherein the particular memory cell is selected to follow the first memory cell in the series of memory cells; and

determining that the particular memory cell is the first erased memory cell in the series in response to the second sense operation of the plurality of sense operations indicating that the particular memory cell is erased.

16. The memory system of claim 15, wherein the memory cells of the series comprise non-volatile memory cells arranged in a two-dimensional array, wherein each of the memory cells of the series comprises a charge storage medium.

17. The memory system of claim 15, wherein the memory cells of the series comprise non-volatile memory cells arranged in a three-dimensional array.

18. The memory system of claim 15, wherein the memory cells of the series comprise multi-state memory cells, each multi-state memory cell capable of being in one of an erased state and one of a plurality of programmed states, wherein:

each of the sense operation of the plurality of sense operations indicates whether the selected memory cell of the series is in the erased state or one of the plurality of programmed states, and

the first voltage potential is configured to cause memory cells of the series in any of the plurality of programmed states to conduct.

19. The memory system of claim 15, wherein each sense operation of the plurality of sense operations comprises sensing a voltage potential on the series of memory cells within a respective sense time period, and wherein the sense time period is less than a read time period associated with a read operation on the series of memory cells.

20. The memory system of claim 15, wherein:

a source end of the series is coupled to a source node and a drain end of the series is coupled to a drain node; and

the controller is configured to program memory cells of the series sequentially from the source end of the series to the drain end of the series.

21. The memory system of claim 15, wherein each sense operation of the plurality of sense operations further comprises applying the second voltage potential to control gates of one or more memory cells of the series following the selected memory cell in the series.

22. The memory system of claim 15, wherein the controller is further configured to:

program memory cells of the series from a first end of the series of memory cells to a second end of the series of memory cells;

select an initial memory cell of the series for an initial sense operation of the plurality of sense operations; and

select the first memory cell of the series for the first sense operation of the plurality of sense operations in response to the initial sense operation indicating that the initial memory cell of the series is programmed, wherein the first memory cell is selected from memory cells of the series between the initial memory cell of the series and the second end of the series.

23. The memory system of claim 15, wherein:

each sense operation further comprises sensing current through the series of memory cells after a first settling time; and

the controller is further configured to perform a read operation to read a designated memory cell of the series, wherein performing the read operation comprises;

applying the first voltage potential to control gates of one or more of the memory cells of the series; and

sensing current through the series of memory cells after a second settling time, the second settling time longer than the first settling time.

25. An apparatus, comprising:

memory logic configured to identify a first erased word line of a memory block comprising a plurality of word lines corresponding to a program order, the memory logic configured to implement a plurality of read iterations on the memory block at respective word line offsets within the program order, wherein performing a read iteration at a current word line offset comprises;

sensing bit lines of the memory block by use of sense circuitry to determine a count of bit lines that are non-conducting while word lines preceding the current word line offset are set to a high read voltage potential, and word lines following the current word line offset are set to a partial read voltage potential,

wherein the high read voltage potential is configured to cause memory cells of the bit lines to conduct, and wherein the partial read voltage potential is configured to cause memory cells of the bit lines that are in an erased state to conduct and to cause memory cells of the bit lines that are in one or more of a plurality of programmed states to be substantially non-conducting;

continuing the plurality of read iterations after the current read iteration in response to the determined count being greater than zero, the continuing comprising determining a next word line offset for a next read iteration of the plurality of read iterations by incrementing the current word line offset in the program order; and

terminating the plurality of read iterations in response to the determined count being equal to zero, the terminating comprising determining that the current word line offset corresponds to the first erased word line of the memory block based on a read iteration preceding the current read iteration in the plurality of read iterations.

26. The apparatus of claim 25, wherein continuing the plurality of read iterations further comprises:

incrementing the current word line offset in the program order by a first number of word lines in the program order in response to the determined count satisfying a first threshold; and

incrementing the current word line offset in the program order by a second number of word lines in the program order in response to the determined count failing to satisfy the first threshold, the second number less than the first number.

27. The apparatus of claim 25, wherein continuing the plurality of read iterations further comprises:

decreasing the partial read voltage potential for the next read iteration such that performing the next read iteration at the next word line offset comprises sensing the bit lines of the memory block while word lines proceeding the next word line offset are set to the high voltage potential, and word lines following the next word line offset are set to the decreased partial read voltage potential,

wherein the decreased partial read voltage potential is configured to cause memory cells of the bit lines that are in an erased state to conduct and to cause memory cells of the bit lines that are in any of the plurality of programmed states to be substantially non-conducting.

28. A system, comprising:

means for performing a first sense operation on a particular word line of a block comprising a plurality of word lines having a sequential program ordering, wherein the first sense operation indicates that memory cells coupled to the particular word line are programmed, and comprises;

applying a first non-selected word line voltage to word lines between the particular word line and a first end of the block, the first non-selected word line voltage configured to cause programmed memory cells to conduct, and

applying a second non-selected word line voltage to word lines between the particular word line and a second end of the block, the second non-selected word line voltage configured to cause erased memory cells to conduct, wherein the second non-selected word line voltage is less than the first non-selected word line voltage;

means for selecting a subsequent word line for a second sense operation in response to the first sense operation indicating that memory cells coupled to the particular word line are programmed, the subsequent word line selected to follow the particular word line in the sequential program ordering; and

means for determining that the particular word line is a last word line programmed in the sequential program ordering in response to the second sense operation indicating that memory cells coupled to the subsequent word line are erased.