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Leveraging chip variability

  • US 9,978,461 B2
  • Filed: 03/17/2017
  • Issued: 05/22/2018
  • Est. Priority Date: 06/18/2010
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a memory controller configured to control the operation of a dynamic random access memory (DRAM) device comprised of memory regions configured to be controlled by the memory controller, the memory controller comprising logic configured to;

    provide an error-likelihood profile comprising error-likelihood metrics respectively corresponding to the memory regions, each error-likelihood metric representing a degree of likelihood that a corresponding memory region will produce a bit error at a given time, the bit error comprising an erroneous toggle of a bit value that is being retained by the DRAM device in the corresponding memory region, wherein the error-likelihood metrics are predictive of potential bit errors in the memory regions represented by the error-likelihood metrics, respectively, and wherein the error-likelihood metrics exist concurrently with respect to each other;

    identify, according to the error-likelihood profile, from among the memory regions, a target memory region, the target memory region identified based on a corresponding error-likelihood metric; and

    based on the identifying, cause a change to an error sensitive factor (ESF) associated with the DRAM device, the ESF comprising a memory refresh rate, wherein the change to the ESF comprises an increase of the memory refresh rate.

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