Leveraging chip variability

• US 9,978,461 B2
• Filed: 03/17/2017
• Issued: 05/22/2018
• Est. Priority Date: 06/18/2010
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Zorn, Benjamin, Bittner, Ray, Kirovski, Darko, Pattabiraman, Karthik
• Primary Examiner(s): Hoang, Tri
• Application Number:
  US15/462,730
• Publication Number:
  US 20170323689A1
• Time in Patent Office: 431 Days
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors

Abstract

Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Claims

1. An apparatus comprising:

a memory controller configured to control the operation of a dynamic random access memory (DRAM) device comprised of memory regions configured to be controlled by the memory controller, the memory controller comprising logic configured to;

provide an error-likelihood profile comprising error-likelihood metrics respectively corresponding to the memory regions, each error-likelihood metric representing a degree of likelihood that a corresponding memory region will produce a bit error at a given time, the bit error comprising an erroneous toggle of a bit value that is being retained by the DRAM device in the corresponding memory region, wherein the error-likelihood metrics are predictive of potential bit errors in the memory regions represented by the error-likelihood metrics, respectively, and wherein the error-likelihood metrics exist concurrently with respect to each other;

identify, according to the error-likelihood profile, from among the memory regions, a target memory region, the target memory region identified based on a corresponding error-likelihood metric; and

based on the identifying, cause a change to an error sensitive factor (ESF) associated with the DRAM device, the ESF comprising a memory refresh rate, wherein the change to the ESF comprises an increase of the memory refresh rate.

2. An apparatus according to claim 1, wherein the target memory region is identified based on its error-likelihood metric indicating a sufficient likelihood of the bit error occurring in association with the target memory region.

3. An apparatus according to claim 1, where each memory region comprises a respective error-likelihood metric.

4. An apparatus according to claim 1, wherein the error-likelihood metrics do not comprise counts of errors.

5. An apparatus according to claim 1, wherein the change to the ESF does not affect all of the memory regions.

6. An apparatus according to claim 1, wherein the causing the change to the ESF does not cause the memory refresh rate increase for all of the memory regions.

7. An apparatus according to claim 1, wherein the increase of the memory refresh rate comprises a decrease in an amount of time between refreshes of one or more of the memory regions.

8. An apparatus according to claim 1, wherein the DRAM device comprises a DRAM chip.

9. An apparatus according to claim 1, wherein the providing the error-likelihood profile comprises computing the error-likelihood profile by the memory controller.

10. An apparatus according to claim 1, wherein the providing the error-likelihood profile comprises accessing the error-likelihood profile on the DRAM device.

11. A method to control operation of a dynamic random access memory (DRAM) device comprised of memory regions, the method comprising:

accessing an error-likelihood function associated with the DRAM device, the error-likelihood function configured to determine that a memory region is likely to fail based on failure prediction metrics of the respective memory regions, each failure prediction metric corresponding to a respective memory-region-specific likelihood of corruption of data being retained by the DRAM device; and

monitoring the failure prediction metrics of the error-likelihood function and identifying the memory region according to the failure prediction metrics; and

according to the identified memory region, changing an operating parameter of the DRAM device, the operating parameter comprising a refresh rate, a frequency, or a voltage of the DRAM device.

12. A method according to claim 11, wherein the DRAM device comprises a memory controller that performs the monitoring.

13. A method according to claim 11, wherein the operating parameter comprises the refresh rate and wherein the change to the refresh rate corresponds to decreasing a time to perform a refresh operation.

14. A method according to claim 11, wherein the monitoring comprises repeatedly checking the failure prediction metrics to identify the memory region.

15. A method according to claim 11, wherein the accessing, the monitoring, and the changing are performed by a memory controller controlling the DRAM device.

16. A method according to claim 11, wherein the failure prediction metrics are repeatedly computed for each respective memory region, and wherein each repeatedly computed failure prediction metric varies over time in correlation with a varying condition of the respective memory region.

17. A dynamic random access memory (DRAM) storage device comprising:

memory regions configured to store data written to the DRAM storage device and to provide data read from the DRAM storage device;

a memory controller configured to control operation of the memory regions;

the DRAM storage device configured to, when operating;

provide a set of error-prediction values for the respective memory regions, each error-prediction value changing in correspondence with probability that a corresponding memory region will be associated with an erroneous bit flip within the memory regions;

select a target memory region according to the error-prediction values; and

based on the target memory region, cause a change to an operating parameter of the DRAM storage device.

18. A DRAM storage device according to claim 17, wherein the error-prediction values are derived by counting accesses to the memory regions.

19. A DRAM storage device according to claim 17, wherein the memory controller is configured to select the target memory region and cause the change to the operating parameter of the DRAM storage device.

20. A DRAM storage device according to claim 17, wherein the operating parameter comprises a refresh rate, a voltage, a frequency, or a setting of the DRAM storage device.

21. A DRAM storage device according to claim 17, wherein each error-prediction value comprises a prediction (i) derived from state of the DRAM storage device, and (ii) about likelihood of a bit error occurring in association with the corresponding memory region.

22. A DRAM storage device according to claim 17, wherein the error-prediction values depend on an error sensitive factor of the DRAM storage device, and wherein the error-prediction values vary according to variation of the error sensitive factor.