Transistor channel

• US 9,978,650 B2
• Filed: 01/06/2015
• Issued: 05/22/2018
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Yu-Hung, Tsai, Ching-Wei, Tu, Yeur-Luen, Lin, Tung-I, Chen, Wei-Li
• Primary Examiner(s): Ward, Eric
• Assistant Examiner(s): Ashbahian, Eric
• Application Number:
  US14/581,970
• Publication Number:
  US 20150108430A1
• Time in Patent Office: 1,232 Days
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A transistor device includes a substrate having a first region and a second region, a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, the first portion being separated from the second portion, a second semiconductor layer of a second semiconductor material over the second portion of the first semiconductor layer, a first transistor of a first conductivity type, the first transistor disposed within the first region and having a first set of source/drain regions formed in the first semiconductor layer, and a second transistor of a second conductivity type, the second transistor disposed within the second region and having a second set of source/drain regions formed in the second semiconductor layer. The second conductivity type is different than the second conductivity type, and the second semiconductor material is different from the first semiconductor material.

Claims

1. A transistor device comprising:

a substrate having a first region and a second region;

a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, the first portion being separated from the second portion wherein the first portion and second portion each extend respectively from a first bottom surface to a first top surface;

a second semiconductor layer of a second semiconductor material over the second portion of the first semiconductor layer, wherein the second semiconductor layer extends from a second bottom surface to a second top surface, the second bottom surface of the second semiconductor layer being disposed above the first top surface of the first portion of the first semiconductor layer;

a first transistor of a first conductivity type, the first transistor disposed within the first region and having a first set of source/drain regions formed in the first semiconductor layer and a first gate structure, wherein the first set of source/drain regions each comprise planar edges that extend to vertexes pointing towards a channel within the first transistor and include a main portion and a tip portion adjacent the vertexes, and wherein the tip portion comprises a superlattice structure and the main portion includes a non-superlattice structure, the superlattice structure alternating between individual layers of silicon germanium and silicon, both the silicon germanium and silicon having a same type of dopant and extending vertically in the tip portion from planar edge to planar edge; and

a second transistor of a second conductivity type, the second transistor disposed within the second region and having a second set of source/drain regions formed in the second semiconductor layer and a second gate structure;

wherein the second conductivity type is different than the first conductivity type, and the second semiconductor material is different from the first semiconductor material; and

wherein the first gate structure is at a first level above the substrate and the second gate structure is at a second level above the substrate, the second level greater than the first level and the first and second levels defined by a bottommost surface of the first and second gate structure respectively.

2. The device of claim 1, wherein the first semiconductor material comprises silicon germanium (SiGe) and the second semiconductor material comprises indium gallium arsenide (InGaAs).

3. The device of claim 1, further comprising, a bonding layer between the first semiconductor layer and the second semiconductor layer over the second region, wherein the bonding layer is disposed over the first top surface of the second portion of the first semiconductor material, and wherein the bonding layer is disposed at a greater height from an underlying substrate than the first top surface of the first portion of the first semiconductor layer.

4. The device of claim 3, wherein the bonding layer comprises an oxide material.

5. The device of claim 1, wherein the first set of source/drain regions and the second set of source drain regions are epitaxially grown.

6. The device of claim 1, wherein the first set of source/drain regions have the same type of dopant of boron.

7. The device of claim 1, wherein the second set of source/drain regions comprise silicon germanium doped with phosphorous.

8. The device of claim 1, wherein the second set of source/drain regions comprise planar edges that extend to vertexes pointing towards a channel within respective transistors.

9. The device of claim 8, wherein each of the first set of source/drain regions and the second set of source/drain regions each include a main portion and a tips of the vertexes portion, wherein the tips of the vertexes portion of the second set of source/drain regions are doped with a higher concentration of a second dopant than the main portions;

and wherein the tips of the vertexes portion of the first set of source/drain regions are doped with a higher concentration of the same type of dopant.

10. The device of claim 8, wherein the second set of source/drain regions each include a main portion and a tip of the vertex portion, and wherein the tip of the vertex portions of the second set of source/drain regions each comprise a superlattice structure and the main portions of the second set of source/drain regions have a non-superlattice structure.

11. The device of claim 10, wherein the superlattice structure of the second set of source/drain regions alternates between individual layers of silicon germanium and silicon, both the silicon germanium and silicon having a same type of second dopant and extending vertically in the tips of each of the second set of source/drain regions from planar edge to planar edge.

12. The device of claim 10, wherein sections of the superlattice structure have a thickness of about 3 nanometers.

13. A transistor device comprising:

a gate stack on a substrate;

a source region disposed in a first recess having two planar surfaces defined by a facet of the substrate having a first crystallographic orientation and angled inwards with respect to the gate stack towards a first vertex pointing towards a channel beneath the gate device; and

a drain region disposed in a second recess having two planar surfaces defined by a facet of the substrate having the first crystallographic orientation and angled inwards with respect to the gate stack towards a second vertex pointing towards the channel;

wherein a tip at the first vertex of the source region comprises a first superlattice structure having a plurality of individual layers that extend up to two planar surfaces of the first recess and the first vertex and a tip at the second vertex of the drain region comprises a second superlattice structure having a plurality of individual layers that extend up to the two planar surfaces of the second recess and the second vertex, wherein the source region and the drain region adjacent the tip of the respective first vertex and second vertex are non-superlattice structure.

14. The device of claim 13, wherein the plurality of individual layers of each of the first and second superlattice structures alternate between silicon germanium and silicon in a direction that is substantially perpendicular to the substrate, both the silicon germanium and silicon having a same type of dopant.

15. The device of claim 13, wherein each of the plurality of the individual layers of the first superlattice structure have a thickness of about 3 nanometers.

16. A semiconductor device comprising:

a first transistor, the first transistor comprising;

a first gate stack disposed over a substrate and on a top surface of a first semiconductor layer;

a first source epitaxial structure doped with a first dopant of boron and filling a first recess in the first semiconductor layer, the first recess having two planar surfaces defined by a facet of the substrate and extending in to a vertex pointing towards a channel beneath the first gate stack, wherein a tip of the vertex of the first source epitaxial structure has a higher concentration of the first dopant than any other portion of the first source epitaxial structure; and

a first drain epitaxial structure doped with the first dopant and filling a second recess in the first semiconductor layer, the second recess having two planar surfaces defined by a facet of the substrate and extending in to a vertex pointing towards the channel, wherein a tip of the vertex of the first drain epitaxial structure has a higher concentration of the first dopant than any other portion of the first drain epitaxial structure, wherein the tip of the vertex of the first source epitaxial structure is spaced apart from the tip of the vertex of the first drain epitaxial structure by a first distance; and

a second transistor, the second transistor comprising

a second gate stack over the substrate and on a top surface of a second semiconductor layer, a portion of the first semiconductor layer underlying the second semiconductor layer;

a second source epitaxial structure doped with a second dopant and filling a third recess in the second semiconductor layer;

a second drain epitaxial structure doped with the second dopant and filling a fourth recess in the second semiconductor layer, wherein a bottom surface of the second semiconductor layer is spaced a greater height from a top surface of the substrate than the top surface of the first semiconductor layer under the first gate stack.

17. The device of claim 16, wherein one of the tip of the vertex of the first source epitaxial structure and the tip of the vertex of the first drain epitaxial structure comprises a superlattice structure that is constrained within the first source epitaxial structure or the first drain epitaxial structure, wherein a portion of the vertex adjacent the superlattice structure has a non-superlattice structure.

18. The device of claim 16, where the first gate stack has a two parallel sides extending above the substrate that intersect two planar surfaces that are defined by a facet on a first crystallographic orientation of the substrate towards a vertex pointing towards the channel, wherein a tip of the vertex of the first gate stack is spaced apart from the tip of the vertex of the first source epitaxial structure by a second distance, wherein the tip of the vertex of the first gate stack is away from the tip of the vertex of the first drain epitaxial structure by the second distance.

19. The device of claim 16, wherein the tip of the vertex of the first source epitaxial structure and the vertex of the first drain epitaxial structure of the first transistor include superlattice structures that alternate between individual layers of silicon germanium and silicon, wherein the individual layers each extend vertically between the two planar surfaces.