Single lead-frame stacked die galvanic isolator

• US 9,978,696 B2
• Filed: 09/14/2016
• Issued: 05/22/2018
• Est. Priority Date: 09/14/2016
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Bernardinis, Gabriele
• Primary Examiner(s): Tran, Tan N
• Application Number:
  US15/265,138
• Publication Number:
  US 20180076154A1
• Time in Patent Office: 615 Days
• Field of Search: 257277, 257531
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06531 Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06537 Electromagnetic shielding
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

Isolators for providing electrical isolation between two circuits operating at different voltages are described, in which multiple semiconductor dies including the isolator components and the components of the two circuits are stacked on top of each other to provide a laterally-compact arrangement. An isolation barrier electrically separates the two circuits, and the isolator may provide a communication channel for transfer of information and/or power between the two circuits. The isolator may be included in an integrated device having a stacked die configuration where a first semiconductor die includes the isolator and components of the first of the two circuits, and a second semiconductor die positioned over the first semiconductor die includes components of the second of the two circuits. Two components of the isolator may be formed in separate layers of the first semiconductor die.

Claims

1. An integrated isolator device comprising:

a single first semiconductor die comprising;

at least one first circuit;

an isolator having a first isolator component positioned in a first layer of the first semiconductor die and coupled to the at least one first circuit, and the isolator further having a second isolator component positioned in a second layer of the first semiconductor die; and

an isolation barrier positioned between the first isolator component and the second isolator component; and

a second semiconductor die positioned over the first semiconductor die, wherein the second semiconductor die has at least one second circuit coupled to the second isolator component.

2. The integrated isolator device of claim 1, wherein the first isolator component is configured to operate at a first voltage and the second isolator component is configured to operate at a second voltage different than the first voltage.

3. The integrated isolator device of claim 2, wherein the at least one first circuit is configured to operate at the first voltage and the at least one second circuit is configured to operate at the second voltage.

4. The integrated isolator device of claim 1, wherein the at least one first circuit includes a transmitter or a receiver and the at least one second circuit includes a transmitter or a receiver.

5. The integrated isolator device of claim 1, wherein the integrated device further comprises a lead frame and the first semiconductor die is mounted on the lead frame.

6. The integrated isolator device of claim 1, wherein the isolator includes a transformer, and the first isolator component and the second isolator component are coils.

7. The integrated isolator device of claim 1, wherein the second semiconductor die and the isolator are non-overlapping.

8. The integrated isolator device of claim 1, wherein the second semiconductor die is positioned over the isolator.

9. The integrated isolator device of claim 8, further comprising at least one via through the second semiconductor die, wherein the at least one via electrically couples the second isolator component to a contact of the second semiconductor die.

10. The integrated isolator device of claim 8, further comprising at least one pillar positioned between the first semiconductor die and the second semiconductor die, wherein the at least one pillar electrically couples the second isolator component to a contact of the second semiconductor die.

11. A method of manufacturing an integrated device having an isolator, the method comprising:

forming a first isolator component of the isolator in a first layer of a first semiconductor die, wherein the first semiconductor die is a single semiconductor die and includes at least one first circuit coupled to the first isolator component;

forming a second isolator component of the isolator in a second layer of the first semiconductor die;

forming an isolation barrier in the first semiconductor die between the first isolator component and the second isolator component; and

positioning a second semiconductor die over the first semiconductor die, wherein the second semiconductor die includes at least one second circuit coupled to the second isolator component.

12. The method of claim 11, wherein positioning the second semiconductor die over the first semiconductor die comprises positioning the second semiconductor die to overlap with the second isolator component of the first semiconductor die.

13. The method of claim 11, further comprising forming a pillar between the first semiconductor die and the second semiconductor die.

14. The method of claim 13, wherein forming the pillar comprises forming the pillar to electrically couple with the second isolator component and a contact of the second semiconductor die.

15. The method of claim 11, further comprising forming a via through a circuitry layer of the second semiconductor die to electrically couple the second isolator component to a contact of the second semiconductor die.

16. A system, comprising:

a single first semiconductor die comprising;

at least one first circuit configured to operate in a first voltage domain;

an isolator having a first isolator component positioned in a first layer of the first semiconductor die and coupled to the at least one first circuit, and the isolator further having a second isolator component positioned in a second layer of the first semiconductor die;

an isolation barrier positioned between the first isolator component and the second isolator component; and

a second semiconductor die positioned over the first semiconductor die, wherein the second semiconductor die has at least one second circuit coupled to the second isolator component and configured to operate in a second voltage domain different than the first voltage domain.

17. The system of claim 16, further comprising a first lead frame on which the first semiconductor die is disposed, wherein an electrical contact on the first semiconductor die is electrically coupled to an electrical contact on the first lead frame, and wherein an electrical contact on the second semiconductor die is electrically coupled to an electrical contact on a second lead frame.

18. The system of claim 16, wherein the second semiconductor die is positioned over the isolator.

19. The system of claim 18, further comprising at least one via through the second semiconductor die, wherein the at least one via electrically couples the second isolator component to a contact of the second semiconductor die.

20. The system of claim 18, further comprising at least one pillar positioned between the first semiconductor die and the second semiconductor die, wherein the at least one pillar electrically couples the second isolator component to a contact of the second semiconductor die.