Wafer backside interconnect structure connected to TSVs

• US 9,978,708 B2
• Filed: 09/19/2016
• Issued: 05/22/2018
• Est. Priority Date: 09/22/2009
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ming-Fa, Chiou, Wen-Chih, Shue, Shau-Lin
• Primary Examiner(s): HO, HOANG QUAN TRAN
• Application Number:
  US15/269,613
• Publication Number:
  US 20170005069A1
• Time in Patent Office: 610 Days
• Field of Search: None
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76841 Barrier, adhesion or liner layers
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05546 Dual damascene structure
• CPC Class Codes: H01L 2224/05547 comprising a core and a coating
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/811 : the bump connector being supplied to the parts to be connected in the bonding apparatus
• CPC Class Codes: H01L 2224/8136 : Bonding interfaces of the semiconductor or solid state body
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

Claims

1. A method for forming an integrated circuit structure, the method comprising:

forming a conductive via in a semiconductor substrate having an active device at a front surface, the semiconductor substrate further having a back surface opposite the front surface;

exposing the conductive via at the back surface of the semiconductor substrate by reducing a thickness of the semiconductor substrate;

after exposing the conductive via at the back surface of the semiconductor substrate, patterning an opening extending from the back surface of the semiconductor substrate into the semiconductor substrate;

forming a first metal feature in the opening and contacting the conductive via; and

forming a bump overlying and electrically connected to the first metal feature relative the back surface of the semiconductor substrate.

2. The method of claim 1, wherein patterning the opening comprises exposing the conductive via, wherein the opening has a greater horizontal dimension than the conductive via, and wherein forming the first metal feature comprises:

forming a dielectric isolation layer on sidewalls and a lateral surface of the opening;

forming a conductive barrier layer on the dielectric isolation layer; and

filling remaining portions of the opening with a metal.

3. The method of claim 2, further comprising, prior to forming the conductive barrier layer, removing a portion of the dielectric isolation layer contacting the conductive via.

4. The method of claim 1, wherein patterning the opening comprises recessing the conductive via so that the back surface of the semiconductor substrate is higher than a surface of the conductive via, and wherein the opening exposes the surface of the conductive via.

5. The method of claim 1 further comprising forming a second metal feature between the first metal feature and the bump.

6. The method of claim 5, wherein the second metal feature comprises a dual damascene structure.

7. The method of claim 5 further comprising forming a dielectric layer on the back surface of the semiconductor substrate, wherein the second metal feature is formed in the dielectric layer.

8. The method of claim 1, wherein horizontal dimensions of the first metal feature are greater than respective horizontal dimensions of the conductive via in a top-down view of the integrated circuit structure.

9. A method comprising:

planarizing a semiconductor substrate to expose a conductive via extending from a front surface of the semiconductor substrate to a back surface of the semiconductor substrate, wherein an active device is disposed at the front surface of the semiconductor substrate;

after exposing the conductive via, etching a trench opening in a semiconductor substrate, wherein the conductive via extends from the trench opening to the front surface of the semiconductor substrate;

depositing a first dielectric liner along sidewalls and a bottom surface of the trench opening;

depositing a conductive barrier layer over the first dielectric liner in the trench opening; and

forming a conductive line in the trench opening over the conductive barrier layer and electrically connected to the conductive via.

10. The method of claim 9 further comprising before etching the trench opening and after exposing the conductive via, recessing the conductive via from a back surface of the semiconductor substrate opposite the front surface.

11. The method of claim 9, wherein at least a portion of the bottom surface of the trench opening is disposed at a different level than a surface of the conductive via exposed by the trench opening.

12. The method of claim 9 further comprising while patterning the trench opening, patterning an additional trench opening in the semiconductor substrate, wherein a portion of the semiconductor substrate is disposed between the trench opening and the additional trench opening.

13. The method of claim 12 further comprising forming an additional conductive line in the additional trench opening.

14. The method of claim 9 further comprising forming an external connector on a surface of the conductive line opposite the conductive via.

15. The method of claim 9 further comprising:

forming a dual-damascene interconnect structure on a surface of the conductive line opposite the conductive via; and

forming an external connector over the dual-damascene interconnect structure.

16. A method comprising:

exposing a conductive via at a back side of a semiconductor substrate, the conductive via extending from the back side of the semiconductor substrate to a front side of the semiconductor substrate, an active device is disposed at the front side of the semiconductor substrate;

after exposing the conductive via, etching a trench opening in the semiconductor substrate, etching the trench opening comprises;

etching the conductive via to define a first opening extending form the back side of the semiconductor substrate into the semiconductor substrate; and

etching the semiconductor substrate to widen the first opening and define the trench opening;

forming a conductive line in the trench opening and electrically connected to the conductive via; and

forming a solder region electrically connected to the conductive line.

17. The method of claim 16, wherein an isolation layer is disposed between a sidewall of the conductive via and the semiconductor substrate, and wherein etching the trench opening comprises removing a portion of the isolation layer exposed by the first opening.

18. The method of claim 16 further comprising:

depositing dielectric isolation layer along sidewalls and a bottom surface of the first opening; and

depositing a conductive barrier layer over the dielectric isolation layer, wherein the conductive barrier layer extends though the dielectric isolation layer, and wherein forming the conductive line comprises forming the conductive line over the conductive barrier layer.

19. The method of claim 18 further comprising removing a portion of the dielectric isolation layer directly over the conductive via using a patterned mask, wherein at least a portion of the patterned mask is disposed in the trench opening.

20. The method of claim 18 further comprising forming a dual-damascene interconnect between the conductive line and the solder region.