Semiconductor device

• US 9,978,757 B2
• Filed: 08/27/2015
• Issued: 05/22/2018
• Est. Priority Date: 12/18/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): Malek, Maliheh
• Application Number:
  US14/837,177
• Publication Number:
  US 20150364477A1
• Time in Patent Office: 999 Days
• Field of Search: 257 68, 257 71, 257213, 257288, 257296-298, 257300, 257306-309, 257311, 257349, 257E27016, 257E27084, 257E27086, 257E27088, 257E27094, 257E21645-E21649, 257906, 438210, 438238, 438239, 438253, 438256
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

Claims

1. A semiconductor device comprising:

a memory cell comprising;

a first transistor;

a second transistor; and

a capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the gate of the first transistor is electrically connected to one of electrodes of the capacitor,

wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,

wherein a first gate of the second transistor is electrically connected to a fourth wiring,

wherein the other of the electrodes of the capacitor is electrically connected to a fifth wiring,

wherein a second gate of the second transistor is electrically connected to a sixth wiring, and

wherein the second transistor comprises an oxide semiconductor layer comprising a channel formation region.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

3. The semiconductor device according to claim 1, wherein a channel formation region of the first transistor is formed of a material other than an oxide semiconductor material.

4. The semiconductor device according to claim 1, wherein a channel formation region of the first transistor is provided in a semiconductor substrate.

5. The semiconductor device according to claim 1, comprising an insulating layer over the first transistor, wherein the second transistor is provided over the insulating layer.

6. The semiconductor device according to claim 5, wherein the capacitor is provided over the insulating layer.

7. The semiconductor device according to claim 1,

wherein the fourth wiring and the sixth wiring are configured to be supplied with a same potential.

8. The semiconductor device according to claim 1,

wherein the fourth wiring and the sixth wiring are configured to be supplied with different potentials from each other.

9. The semiconductor device according to claim 1, wherein, in the second transistor, the first gate and the second gate face each other with the oxide semiconductor layer comprising the channel formation region interposed between the first gate and the second gate.

10. The semiconductor device according to claim 1, wherein, in the second transistor, the first gate and the second gate are respectively located over and below the oxide semiconductor layer comprising the channel formation region.

11. A semiconductor device comprising:

a first transistor;

a second transistor; and

a capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the gate of the first transistor is electrically connected to one of electrodes of the capacitor,

wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,

wherein a first gate of the second transistor is electrically connected to a fourth wiring,

wherein the other of the electrodes of the capacitor is electrically connected to a fifth wiring,

wherein a second gate of the second transistor is electrically connected to a sixth wiring,

wherein the second transistor comprises an oxide semiconductor layer comprising a channel formation region, and

wherein, in the second transistor, the first gate and the second gate face each other with the oxide semiconductor layer comprising the channel formation region interposed between the first gate and the second gate.

12. The semiconductor device according to claim 11, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

13. The semiconductor device according to claim 11, wherein a channel formation region of the first transistor is formed of a material other than an oxide semiconductor material.

14. The semiconductor device according to claim 11, wherein a channel formation region of the first transistor is provided in a semiconductor substrate.

15. The semiconductor device according to claim 11, comprising an insulating layer over the first transistor, wherein the second transistor is provided over the insulating layer.

16. The semiconductor device according to claim 15, wherein the capacitor is provided over the insulating layer.

17. The semiconductor device according to claim 11, wherein the fourth wiring and the sixth wiring are configured to be supplied with a same potential.

18. The semiconductor device according to claim 11, wherein the fourth wiring and the sixth wiring are configured to be supplied with potentials different from each other.

19. A semiconductor device comprising:

a first transistor;

a second transistor; and

a capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,

wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,

wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,

wherein the gate of the first transistor is electrically connected to one of electrodes of the capacitor,

wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring,

wherein a first gate of the second transistor is electrically connected to a fourth wiring,

wherein the other of the electrodes of the capacitor is electrically connected to a fifth wiring,

wherein a second gate of the second transistor is electrically connected to a sixth wiring,

wherein the second transistor comprises an oxide semiconductor layer comprising a channel formation region, and

wherein, in the second transistor, the first gate and the second gate are respectively located over and below the oxide semiconductor layer comprising the channel formation region.

20. The semiconductor device according to claim 19, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

21. The semiconductor device according to claim 19, wherein a channel formation region of the first transistor is formed of a material other than an oxide semiconductor material.

22. The semiconductor device according to claim 19, wherein a channel formation region of the first transistor is provided in a semiconductor substrate.

23. The semiconductor device according to claim 19, comprising an insulating layer over the first transistor, wherein the second transistor is provided over the insulating layer.

24. The semiconductor device according to claim 23, wherein the capacitor is provided over the insulating layer.

25. The semiconductor device according to claim 19, wherein the fourth wiring and the sixth wiring are configured to be supplied with a same potential.

26. The semiconductor device according to claim 19, wherein the fourth wiring and the sixth wiring are configured to be supplied with potentials different from each other.