Pads and pin-outs in three dimensional integrated circuits
First Claim
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1. A plurality of semiconductor devices, comprising:
- a programmable device including a first programmable layer, a memory layer operable to program the first programmable layer with a logical functionality, and a first pad layer including a plurality of input/output characteristics and a plurality of pads in an arrangement; and
a hard-wired device including a second programmable layer with common design relative to the first programmable layer, a hard-wire layer operable to hard-wire the second programmable layer with the logical functionality, and a second pad layer with common design relative to the first pad layer.
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Abstract
A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.
198 Citations
20 Claims
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1. A plurality of semiconductor devices, comprising:
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a programmable device including a first programmable layer, a memory layer operable to program the first programmable layer with a logical functionality, and a first pad layer including a plurality of input/output characteristics and a plurality of pads in an arrangement; and a hard-wired device including a second programmable layer with common design relative to the first programmable layer, a hard-wire layer operable to hard-wire the second programmable layer with the logical functionality, and a second pad layer with common design relative to the first pad layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An apparatus, comprising:
a pad interface circuit operable with a programmable device and further operable with a hard-wired device, wherein the programmable device and the hard-wired device are interchangeable, and wherein; the programmable device includes a first programmable layer, a memory layer operable to program the first programmable layer with a logical functionality, and a first pad layer operable with the pad interface circuit; and the hard-wired device includes a second programmable layer with common design relative to the first programmable layer, a hard-wire layer operable to hard-wire the second programmable layer with the logical functionality, and a second pad layer with common design relative to the first pad layer and operable with the pad interface circuit. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An apparatus, comprising:
a peripheral device operable with a programmable device, further operable with a hard-wired device, and including an interface configuration, wherein the programmable device and the hard-wired device are interchangeable, and wherein; the programmable device includes a first programmable layer, a memory layer operable to program the first programmable layer with a logical functionality, and a first pad layer operable with the interface configuration; and the hard-wired device includes a second programmable layer with common design relative to the first programmable layer, a hard-wire layer operable to hard-wire the second programmable layer with the logical functionality, and a second pad layer with common design relative to the first pad layer and operable with the interface configuration. - View Dependent Claims (16, 17, 18, 19, 20)
Specification