Semiconductor device with non-uniform trench oxide layer

• US 9,978,859 B2
• Filed: 06/05/2017
• Issued: 05/22/2018
• Est. Priority Date: 07/08/2015
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Park, Chanho, Shibib, Ayman, Terrill, Kyle
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US15/614,257
• Publication Number:
  US 20170271498A1
• Time in Patent Office: 351 Days
• Field of Search: 438259, 438268, 438270, 257328, 257329, 257330, 257333, 257E21218, 257E21252, 257E21359, 257E29021, 257E29118, 257E29133
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device includes a trench formed in an epitaxial layer and an oxide layer that lines the sidewalls of the trench. The thickness of the oxide layer is non-uniform, so that the thickness of the oxide layer toward the top of the trench is thinner than it is toward the bottom of the trench. The epitaxial layer can have a non-uniform dopant concentration, where the dopant concentration varies according to the thickness of the oxide layer.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a first trench in an epitaxial layer, the first trench having a bottom and sidewalls;

depositing an oxide layer across the bottom and on the sidewalls of the first trench;

depositing material within the first trench to cover a first portion of the oxide layer and leaving a second portion of the oxide layer exposed;

removing some of the oxide layer in the second portion, wherein after said removing the second portion of the oxide layer has a thickness that is less than a thickness of the first portion of the oxide layer;

depositing the material in the first trench to cover the second portion of the oxide layer;

forming a source electrode in contact with the material in the first trench; and

adding dopant outside the first trench to the epitaxial layer to produce a non-uniform concentration of the dopant in the epitaxial layer outside the first trench, wherein the non-uniform concentration of the dopant in the epitaxial layer varies according to the thickness of the oxide layer inside the first trench and adjacent thereto.

2. The method of claim 1, further comprising:

adding dopant to a first region of the epitaxial layer outside the first trench at a depth corresponding to the first portion of the oxide layer to produce a first dopant concentration in the first region; and

adding the dopant to a second region of the epitaxial layer outside the first trench at a depth corresponding to the second portion of the oxide layer to produce a second dopant concentration in the second region.

3. The method of claim 2, wherein the first dopant concentration is less than the second dopant concentration.

4. The method of claim 1, wherein the thickness of the oxide layer decreases linearly through the first portion of the oxide layer and decreases linearly through the second portion of the oxide layer.

5. The method of claim 1, wherein the first portion of the oxide layer has a uniform first thickness, and wherein the second portion of the oxide layer has a uniform second thickness, the second thickness less than the first thickness.

6. The method of claim 1, further comprising forming a structure adjacent to the first trench, the structure comprising:

a second trench filled with material, a body region, and a source region.