Radiation tolerant, analog latch peak current mode control for power converters

• US 9,979,285 B1
• Filed: 10/17/2017
• Issued: 05/22/2018
• Est. Priority Date: 10/17/2017
• Status: Active Grant

• Current Assignee: Crane Electronics, Inc. (Crane Company)
• Original Assignee: Crane Electronics, Inc. (Crane Company)
• Inventors: Lam, Cuon, Nguyen, Hach, Nguyen, Khoa, Odell, Peter, Song, Sovann
• Primary Examiner(s): Dole, Timothy J
• Assistant Examiner(s): Andino, Ivan Laboy
• Application Number:
  US15/786,368
• Time in Patent Office: 217 Days
• Field of Search: 323271, 323282-285, 323351
• CPC Class Codes: H02J 3/18 Arrangements for adjusting, eliminating or compensating reactive power in networks for adjustment of voltage H02J3/16
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/4208 Arrangements for improving power factor of AC input
• CPC Class Codes: H02M 1/44 Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H02M 3/33592 having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Systems and methods for providing peak current mode control (PCMC) for power converters using discrete analog components. Peak current mode control functionality for latching, set, reset, clocking and slope compensation is provided via available analog components that provide improved performance, design flexibility, reliability, and radiation tolerance. Discrete analog components may include analog comparators, resistors, capacitors, diodes, etc.

Claims

1. A peak current mode control (PCMC) controller for a power converter, the power converter comprising one or more controllable switches that selectively electrically couples a power source to a load, the PCMC controller comprising:

a latch circuit comprising an analog comparator and a latching capacitor, the analog comparator comprising a first input node coupled to the latching capacitor, a second input node coupled to a latch circuit reference voltage circuit, and an output node;

a peak current detector circuit comprising an analog comparator having a first input node coupled to a current sensor circuit that, in operation, senses a current of the power converter, a second input node coupled to an error control signal circuit, and an output node coupled to the latching capacitor, in operation the peak current detector circuit compares a current sensor signal received from the current sensor circuit to an error control signal received from the error control signal circuit and, responsive to detecting that the current sensor signal exceeds the error control signal, causes the latching capacitor to discharge;

a clock circuit comprising an analog comparator, in operation, the clock circuit generates a clock signal at a clock signal node and a charge signal at a charge signal node, the charge signal node being coupled to the latching capacitor to selectively charge the latching capacitor; and

a gate circuit comprising an analog comparator having a first input node coupled to a gate circuit reference voltage circuit, a second input node coupled to the clock signal node and to the output node of the analog comparator of the latch circuit via an OR-circuit, and an output node that, in operation, provides a control signal to the one or more controllable switches of the power converter.

2. The PCMC controller of claim 1, further comprising:

a slope compensation circuit comprising an input node coupled to the clock signal node, and an output node coupled to the first input node of the analog comparator of the peak current detector circuit.

3. The PCMC controller of claim 1, further comprising:

a current sensor circuit comprising a current transducer that, in operation, senses a current of the power converter.

4. The PCMC controller of claim 3 wherein the current transducer comprises a transformer or a resistor.

5. The PCMC controller of claim 1 wherein the OR-circuit comprises a plurality of diodes.

6. The PCMC controller of claim 1 wherein the analog comparator of the clock circuit comprises first and second complementary output nodes, the clock signal is generated at the first output node and the charge signal is generated at the second output node.

7. The PCMC controller of claim 1 wherein the output node of the peak current detector circuit is coupled to the latching capacitor via a diode.

8. The PCMC controller of claim 1 wherein the charge signal node of the clock circuit is coupled to the latching capacitor via a diode and a resistor coupled together in series.

9. A power converter, comprising:

a transformer having a primary winding and a secondary winding, the primary winding electrically coupleable to an input voltage node and the secondary winding electrically coupleable to an output voltage node;

a primary circuit electrically coupled to the primary winding, the primary winding comprising at least one controllable switch; and

a peak current mode control (PCMC) controller, comprising;

a latch circuit comprising an analog comparator and a latching capacitor, the analog comparator comprising a first input node coupled to the latching capacitor, a second input node coupled to a latch circuit reference voltage circuit, and an output node;

a peak current detector circuit comprising an analog comparator having a first input node coupled to a current sensor circuit that, in operation, senses a current of the power converter, a second input node coupled to an error control signal circuit, and an output node coupled to the latching capacitor, in operation the peak current detector circuit compares a current sensor signal received from the current sensor circuit to an error control signal received from the error control signal circuit and, responsive to detecting that the current sensor signal exceeds the error control signal, causes the latching capacitor to discharge;

a clock circuit comprising an analog comparator, in operation, the clock circuit generates a clock signal at a clock signal node and a charge signal at a charge signal node, the charge signal node coupled to the latching capacitor to selectively charge the latching capacitor; and

a gate circuit comprising an analog comparator having a first input node coupled to a gate circuit reference voltage circuit, a second input node coupled to the clock signal and the output node of the analog comparator of the latch circuit via an OR-circuit, and an output node that, in operation, provides a control signal to the one or more controllable switches of the power converter.

10. The power converter of claim 9 wherein the PCMC controller further comprises a slope compensation circuit comprising an input node coupled to the clock signal node, and an output node coupled to the first input node of the analog comparator of the peak current detector circuit.

11. The power converter of claim 9, further comprising:

a current sensor circuit comprising a current transducer that, in operation, senses a current of the power converter.

12. The power converter of claim 9 wherein the output of the peak current detector circuit is coupled to the latching capacitor via a diode, and the charge signal of the clock circuit is coupled to the latching capacitor via a diode and a resistor coupled together in series.

13. A peak current mode control (PCMC) controller for a power converter that, in operation, controls the power converter according to peak current mode control, the power converter comprising one or more controllable switches, the PCMC controller comprising:

an analog latch circuit comprising an input and an output, the input coupled to a latching capacitor;

an analog peak current detector circuit comprising an output coupled to the latching capacitor, in operation the analog peak current detector circuit compares a current sensor signal to an error control signal and, responsive to detecting that the current sensor signal exceeds the error control signal, causes the latching capacitor of the analog latch circuit to discharge;

an analog clock circuit that, in operation, generates a clock signal and a charge signal, the charge signal coupled to the latching capacitor to selectively charge the latching capacitor; and

an analog gate circuit having an input coupled to the clock signal and the output of the analog latch circuit via an OR-circuit, and an output that, in operation, provides a control signal to the one or more controllable switches of the power converter.

14. The PCMC controller of claim 13, further comprising:

a slope compensation circuit comprising an input coupled to the clock signal, and an output coupled to the current sensor signal.

15. The PCMC controller of claim 13, further comprising:

an analog current sensor circuit comprising a current transducer that, in operation, senses a current of the power converter.

16. The PCMC controller of claim 15 wherein the current transducer comprises a transformer or a resistor.

17. The PCMC controller of claim 13 wherein the OR-circuit comprises a plurality of diodes.

18. The PCMC controller of claim 13 wherein the analog clock circuit comprises first and second complementary outputs, the clock signal is generated by the first output and the charge signal is generated by the second output.

19. The PCMC controller of claim 13 wherein the output of the analog peak current detector circuit is coupled to the latching capacitor via a diode.

20. The PCMC controller of claim 13 wherein the charge signal of the analog clock circuit is coupled to the latching capacitor via a diode and a resistor coupled together in series.