Smooth transitioning buck-boost DC-DC converter

• US 9,979,295 B2
• Filed: 04/03/2017
• Issued: 05/22/2018
• Est. Priority Date: 07/24/2014
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Inventors: Kay, Michael R., Nag, Manbir Singh
• Primary Examiner(s): Tran, Nguyen
• Application Number:
  US15/477,579
• Publication Number:
  US 20170207705A1
• Time in Patent Office: 414 Days
• Field of Search: 323222, 323259, 323271, 323282-285
• CPC Class Codes: H02M 1/0003 Details of control, feedback or regulation circuits
• CPC Class Codes: H02M 1/0045 Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
• CPC Class Codes: H02M 1/4291 by using a Buck converter to switch the input current
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1586 switched with a phase shift, i.e. interleaved
• CPC Class Codes: H03F 3/38 DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers switched capacitor amplifiers H03F3/005

Abstract

A buck-boost DC-DC converter, which includes converter control circuitry, converter switching circuitry, and a first inductive element, is disclosed. The converter control circuitry provides a buck mode timing signal and a boost mode timing signal. The converter switching circuitry provides a switching output signal. During a buck mode of the buck-boost DC-DC converter, when a buck pulse-width of the switching output signal is less than a buck pulse-width threshold, the buck pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. During a boost mode of the buck-boost DC-DC converter, when a boost pulse-width of the switching output signal is less than a boost pulse-width threshold, the boost pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal. The first inductive element receives and filters the switching output signal to provide a converter output signal.

Claims

1. Circuitry configured to operate in both a first mode and a second mode, and comprising:

control circuitry configured to provide a first mode timing signal and a second mode timing signal; and

switching circuitry configured to provide a switching output signal, wherein;

during the first mode, when a first pulse-width of the switching output signal is less than a first pulse-width threshold, the first pulse-width is limited based on both the first mode timing signal and the second mode timing signal; and

during the second mode, when a second pulse-width of the switching output signal is less than a second pulse-width threshold, the second pulse-width is limited based on both the first mode timing signal and the second mode timing signal.

2. The circuitry of claim 1 further comprising a buck-boost DC-DC converter, which comprises the control circuitry, the switching circuitry, and a first inductive element, wherein:

the buck-boost DC-DC converter is configured to operate in both the first mode and the second mode;

the first mode is a buck mode and the second mode is a boost mode;

the control circuitry is converter control circuitry;

the switching circuitry is converter switching circuitry;

the first mode timing signal is a buck mode timing signal;

the second mode timing signal is a boost mode timing signal;

the first pulse-width is a buck pulse-width;

the second pulse-width is a boost pulse-width;

the first pulse-width threshold is a buck pulse-width threshold;

the second pulse-width threshold is a boost pulse-width threshold; and

the first inductive element is configured to receive and filter the switching output signal to provide a converter output signal.

3. The circuitry of claim 2 wherein the buck-boost DC-DC converter further comprises a first capacitive element, such that the first inductive element and the first capacitive element are coupled in series between the converter switching circuitry and ground to form a lowpass filter.

4. The circuitry of claim 2 wherein a DC power source is configured to provide a DC source signal to the converter control circuitry and the converter switching circuitry.

5. The circuitry of claim 4 wherein the converter control circuitry is further configured to select the one of the buck mode and the boost mode based on a DC source voltage of the DC source signal and a setpoint of a converter output voltage of the converter output signal.

6. The circuitry of claim 2 wherein the converter control circuitry is further configured to select the buck mode when a setpoint of a converter output voltage of the converter output signal is less than a DC source voltage, and select the boost mode when the setpoint of the converter output voltage is greater than the DC source voltage.

7. The circuitry of claim 2 wherein during the buck mode, when the buck pulse-width of the switching output signal is greater than the buck pulse-width threshold, the buck pulse-width is not limited based on the boost mode timing signal;

and during the boost mode, when the boost pulse-width of the switching output signal is greater than the boost pulse-width threshold, the boost pulse-width is not limited based on the buck mode timing signal.

8. The circuitry of claim 2 wherein during the buck mode, the switching output signal toggles between being based on ground and being based on a DC source signal, such that a switching output voltage of the switching output signal toggles between nominally zero volts and nominally a DC source voltage of the DC source signal.

9. The circuitry of claim 2 further comprising a boost mode power supply configured to provide a boost supply signal having a boost supply voltage.

10. The circuitry of claim 9 wherein the boost mode power supply comprises a capacitor-based charge pump.

11. The circuitry of claim 9 wherein during the buck mode, the switching output signal toggles between being based on the boost supply signal and being based on ground, such that the boost supply voltage is nominally equal to a DC source voltage of a DC source signal, such that a switching output voltage of the switching output signal toggles between nominally zero volts and nominally the DC source voltage.

12. The circuitry of claim 9 wherein during the boost mode, the switching output signal toggles between being based on the boost supply signal and being based on a DC source signal, such that the boost supply voltage is nominally equal to 1.5 times a DC source voltage of the DC source signal, wherein a switching output voltage of the switching output signal toggles between nominally the DC source voltage and nominally 1.5 times the DC source voltage.

13. The circuitry of claim 9 wherein during the boost mode, the switching output signal toggles between being based on the boost supply signal and being based on a DC source signal, such that the boost supply voltage is nominally equal to 2 times a DC source voltage of the DC source signal, wherein a switching output voltage of the switching output signal toggles between nominally the DC source voltage and nominally 2 times the DC source voltage.

14. The circuitry of claim 2 wherein a linear amplifier is configured to at least partially provide an envelope power supply signal to a radio frequency (RF) power amplifier (PA) using the converter output signal.

15. The circuitry of claim 14 wherein the linear amplifier is further configured to regulate a voltage of the envelope power supply signal based on a setpoint of the envelope power supply signal.

16. The circuitry of claim 15 wherein the envelope power supply signal is amplitude modulated to provide at least partial envelope tracking of an RF transmit signal from the RF PA.

17. The circuitry of claim 16 wherein a bandwidth of the envelope power supply signal is greater than 10 megahertz.

18. The circuitry of claim 14 wherein a switching supply is configured to at least partially provide the envelope power supply signal.

19. The circuitry of claim 14 wherein the RF PA is configured to receive and amplify an RF input signal to provide an RF transmit signal using the envelope power supply signal, which provides power for amplification.

20. The circuitry of claim 14 wherein the converter output signal is based on a maximum amplitude of the envelope power supply signal.