Integrated delay modules

• US 9,979,374 B2
• Filed: 04/25/2017
• Issued: 05/22/2018
• Est. Priority Date: 04/25/2016
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Kumu Networks, Inc.
• Inventors: Hahn, Wilhelm Steffen, Riddle, Alfred, Landi, Ernie
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US15/496,948
• Publication Number:
  US 20170310295A1
• Time in Patent Office: 392 Days
• Field of Search: 333109, 333111, 333160, 333156, 327551-559
• CPC Class Codes: H03H 7/0115 comprising only inductors and capacitors H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence
• CPC Class Codes: H03H 7/32 with lumped inductance and capacitance

Abstract

An analog time delay filter circuit including a first delay circuit block arranged in a modular layout, having a first time delay filter, a first input, a first output, and first and second pass-throughs; a second delay circuit block arranged in the same modular layout, having a second time delay filter, a second input, a second output, and third and fourth pass-throughs; and an interposer circuit block that electrically couples the second input to the first pass-through and the second output to the second pass-through.

Claims

1. An analog time delay filter circuit comprising:

a first delay circuit block, comprising;

a first time delay filter having at least one LC resonator;

a first input, electrically coupled to the first time delay filter;

a first output, electrically coupled to the first time delay filter;

a first circuit pass-through; and

a second circuit pass-through;

wherein the first output, the first input, the first circuit pass-through, and the second circuit pass-through intersect a first surface of the first delay circuit block according to a first modular layout;

a second delay circuit block, comprising;

a second time delay filter having at least one LC resonator;

a second input, electrically coupled to the second time delay filter;

a second output, electrically coupled to the second time delay filter;

a third circuit pass-through; and

a fourth circuit pass-through;

wherein the second output, the second input, the third circuit pass-through, and the fourth circuit pass-through intersect a third surface of the second delay circuit block according to a second modular layout;

wherein the first and second modular layouts are identical; and

an interposer circuit block that electrically couples the second input to the first circuit pass-through and the second output to the second circuit pass-through.

2. The analog time delay filter circuit of claim 1, wherein the first delay circuit block further comprises a second planar surface;

wherein the second delay circuit block comprises a fourth planar surface;

wherein the first, second, third, and fourth surfaces are parallel;

wherein the second surface is also intersected by the second circuit pass-throughs;

wherein the fourth surface is also intersected by the third and fourth circuit pass-throughs;

wherein the interposer circuit block electrically couples to the first and second circuit pass-throughs at the second surface and to the second input and second output at the third surface.

3. The analog time delay filter circuit of claim 2, wherein the analog time delay filter circuit is a laminate structure having a set of layers;

wherein the first delay circuit block is constructed from a first subset of the set of layers;

wherein the interposer circuit block is constructed from a second subset of the set of layers;

wherein the second delay circuit block is constructed from a third subset of the set of layers;

wherein the first, second, and third subsets are non-overlapping subsets.

4. The analog time delay filter circuit of claim 3, wherein the first delay circuit block, the second delay circuit block, and the interposer circuit block share a first vertical ground wall.

5. The analog time delay filter circuit of claim 4, further comprising a third delay circuit block, constructed from the first subset of the set of layers;

further comprising a fourth delay circuit block, constructed from the third subset of the set of layers;

wherein the third delay circuit block is adjacent to and shares a second vertical ground wall with the first delay circuit block;

wherein the fourth delay circuit block is adjacent to and shares a third vertical ground wall with the second delay circuit block.

6. The analog time delay filter circuit of claim 5, wherein the second and third vertical ground walls are electrically coupled.

7. The analog time delay filter circuit of claim 5, wherein the second and third vertical ground walls comprise first and second sets of vias, respectively;

wherein the first set of vias extends through the first subset of layers;

wherein the second set of vias extends through the third subset of layers.

8. The analog time delay filter circuit of claim 3, wherein the first delay circuit block comprises:

a substrate comprising a first isolative layer, the first isolative layer comprising a first surface and a second surface, the second surface substantially parallel to the first surface;

a resonator, comprising a capacitive element coupled to an inductive element, the inductive element comprising;

a first conductive region coupled to the first surface of the first isolative layer,

a second conductive region coupled to the second surface of the first isolative layer,

a first via that is electrically coupled to and extends between the first and second conductive region;

a second via that is electrically coupled to and extends between the first conductive region and a first portion of the capacitive element; and

a third via that is electrically coupled to and extends between the second conductive region and a second portion of the capacitive element;

wherein the first conductive region, the first via, the second conductive region, the second via, the capacitive element, and the third via form a loop;

a first coupling point, electrically coupled to the first conductive region of the resonator; and

a second coupling point, electrically coupled to the second conductive region of the resonator.

9. The analog time delay filter circuit of claim 8, wherein the first portion of the capacitive element comprises a first conductive planar region, the second portion of the capacitive element comprises a second conductive planar region, and the second portions are substantially parallel.

10. The analog time delay filter circuit of claim 2, further comprising a coupling circuit block, the coupling circuit block having a fifth planar surface parallel to the first, second, third, and fourth planar surfaces;

wherein the coupling circuit block comprises;

a first electrical contact, electrically coupled to the first input of the first delay circuit block;

a second electrical contact, electrically coupled to the first output of the first delay circuit block and to the second input of the second delay circuit block; and

a third electrical contact, electrically coupled to the second output of the second delay circuit block.

11. The analog time delay filter circuit of claim 10, wherein the second electrical contact is coupled to the second input via the first circuit pass-through;

wherein the third electrical contact is coupled to the second output via the second circuit pass-through.

12. The analog time delay filter circuit of claim 11 further comprising:

a third delay circuit block, comprising;

a third time delay filter having at least one LC resonator;

a third input, electrically coupled to the third time delay filter; and

a third output, electrically coupled to the third time delay filter; and

a fourth delay circuit block, comprising;

a fourth time delay filter having at least one LC resonator;

a fourth input, electrically coupled to the fourth time delay filter; and

a fourth output, electrically coupled to the fourth time delay filter;

wherein the third electrical contact of the coupling circuit block is coupled to both of the second output and the third input;

wherein the coupling circuit block further comprises a fourth electrical contact, the fourth contact coupled to both of the third output and the fourth input, and a fifth electrical contact, the fifth electrical contact coupled to the fourth output.

13. The analog time delay filter circuit of claim 12, wherein the coupling circuit block further comprises a first bridging contact, coupled to the first output, and a second bridging contact, coupled to the fourth input.

14. The analog time delay filter circuit of claim 13, wherein the first bridging contact and the second bridging contact are electrically coupled by solder.

15. The analog time delay filter circuit of claim 13, wherein the first bridging contact and the second bridging contact are removably electrically coupled by a switch.

16. The analog time delay filter circuit of claim 11 further comprising:

a third delay circuit block, comprising;

a third time delay filter having at least one LC resonator;

a third input, electrically coupled to the third time delay filter; and

a third output, electrically coupled to the third time delay filter; and

a fourth delay circuit block, comprising;

a fourth time delay filter having at least one LC resonator;

a fourth input, electrically coupled to the fourth time delay filter; and

a fourth output, electrically coupled to the fourth time delay filter; and

an amplifier, having an amplifier input and an amplifier output, the amplifier input electrically coupled to the second output and the amplifier output electrically coupled to the third input;

wherein the coupling circuit block further comprises a fourth electrical contact, the fourth contact coupled to both of the third output and the fourth input, and a fifth electrical contact, the fifth electrical contact coupled to the fourth output.

17. The analog time delay filter circuit of claim 16, wherein the coupling circuit block further comprises a first bridging contact, coupled to the amplifier input, and a second bridging contact, coupled to the amplifier output.

18. The analog time delay filter circuit of claim 17, wherein the first bridging contact and the second bridging contact are electrically coupled by solder, resulting in an electrical shorting of the amplifier.

19. The analog time delay filter circuit of claim 17, wherein the first bridging contact and the second bridging contact are removably electrically coupled by a switch.