Apparatus and methods for phase synchronization of phase-locked loops

• US 9,979,408 B2
• Filed: 05/05/2016
• Issued: 05/22/2018
• Est. Priority Date: 05/05/2016
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Mayer, Christopher, McLaurin, David J., Angell, Christopher W., Desai, Sudhir, Bal, Steven R.
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Mattison, David
• Application Number:
  US15/147,408
• Publication Number:
  US 20170324419A1
• Time in Patent Office: 747 Days
• Field of Search: 327107
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers
• CPC Class Codes: H03L 7/235 Nested phase locked loops
• CPC Class Codes: H04B 7/0413 MIMO systems
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.

Claims

1. A radio frequency (RF) communication system comprising:

a phase-locked loop (PLL) configured to generate one or more output clock signals;

a sampling circuit configured to generate a plurality of samples by sampling the one or more output clock signals based on timing of a reference clock signal;

a phase difference calculation circuit configured to generate a phase difference signal based on the plurality of samples and a tracking digital phase signal representing the phase of the PLL; and

a phase adjustment control circuit configured to provide a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.

2. The RF communication system of claim 1, further comprising a phase accumulator configured to generate the tracking digital phase signal, wherein the phase accumulator updates a value of the tracking digital phase signal based on a fractional frequency tuning signal and the timing of the reference clock signal.

3. The RF communication system of claim 1, wherein the one or more output clock signals comprise an in-phase (I) local oscillator signal and a quadrature-phase (Q) local oscillator signal, wherein the sampling circuit comprises a first sampler configured to generate an I sample signal by sampling the I local oscillator signal based on timing of the reference clock signal, and a second sampler configured to generate a Q sample signal by sampling the Q local oscillator signal based on timing of the reference clock signal.

4. The RF communication system of claim 3, wherein the phase difference calculation circuit comprises:

a numerically controlled oscillator (NCO) configured to generate an I phase signal and a Q phase signal based on the tracking digital phase signal; and

an accumulated phase difference calculator configured to generate the phase difference signal based on accumulating a plurality of cross-multiplications of a first complex signal and a complex conjugate of a second complex signal, wherein the first complex signal comprises the I phase signal and the Q phase signal, and wherein the second complex signal comprises the I sample signal and the Q sample signal.

5. The RF communication system of claim 4, wherein the phase adjustment control circuit is operable in a selected operating mode chosen from a plurality of operating modes including an initial calibration mode and a tracking calibration mode, wherein the phase adjustment control circuit is further configured to change a resolution of the NCO based on the selected operating mode.

6. The RF communication system of claim 4, wherein the phase difference calculation circuit generates the phase difference signal based on only one of the I sample signal or the Q sample signal in a tracking calibration mode.

7. The RF communication system of claim 6, wherein the phase adjustment control circuit is further configured to determine a direction of phase adjustment in the tracking calibration mode based on counting a number of positive samples and a number of negative samples of the I sample signal or the Q sample signal.

8. The RF communication system of claim 1, further comprising a master phase control circuit configured to generate a master digital phase signal, wherein the phase adjustment control circuit is further configured to provide the phase adjustment to the PLL based on the master digital phase signal.

9. The RF communication system of claim 8, wherein the master phase control circuit comprises:

a master counter configured to generate a master count signal based on the timing of the reference clock signal and a synchronization signal; and

a master phase calculation circuit configured to generate an instantaneous master phase signal based on a fractional frequency tuning signal and the master count signal.

10. The RF communication system of claim 9, wherein the master phase control circuit further comprises a master phase accumulator configured to generate the master digital phase signal, wherein the master phase accumulator is initialized by the instantaneous master phase signal, and updates the master digital phase signal based on the fractional frequency tuning signal and the timing of the reference clock signal.

11. The RF communication system of claim 9, wherein the master counter is resettable by the synchronization signal.

12. The RF communication system of claim 1, further comprising a mixer configured to provide mixing based on the one or more output clock signals from the PLL.

13. The RF communication system of claim 1, wherein the phase adjustment control circuit provides the phase adjustment to the PLL in increments over a plurality of cycles of the reference clock signal.

14. The RF communication system of claim 1, wherein the PLL comprises a modulator configured to control a division rate of the PLL, wherein the phase adjustment control circuit is configured to provide the phase adjustment to the PLL based on applying a phase offset to the modulator.

15. The RF communication system of claim 1, wherein the phase adjustment control circuit changes a frequency of the PLL during an initial calibration mode.

16. The RF communication system of claim 15, wherein the phase adjustment control circuit is further configured to vary the frequency of the PLL to statistically decorrelate the plurality of samples during the initial calibration mode.

17. The RF communication system of claim 15, wherein the phase adjustment control circuit iteratively adjusts the phase of the PLL during an initial calibration mode to determine a phase at which a phase detector changes direction.

18. The RF communication system of claim 15, wherein the PLL further comprises:

a tracking phase accumulator configured to generate the tracking digital phase signal representing the phase of the PLL, wherein the tracking phase accumulator and the PLL operate using a modified fractional frequency tuning signal during the initial calibration mode; and

a master phase control circuit configured to generate a master digital phase signal based on an unmodified fractional frequency tuning signal.

19. A method of phase synchronization in a frequency synthesizer, the method comprising:

generating one or more output clock signals using a phase-locked loop (PLL);

sampling the one or more output clock signals based on timing of a reference clock signal to generate a plurality of samples;

generating a phase difference signal based on the plurality of samples and a tracking digital phase signal representing a phase of the PLL; and

synchronizing the PLL by providing a phase adjustment that is based on the phase difference signal.

20. The method of claim 19, further comprising changing a frequency of the PLL during an initial calibration mode.

21. The method of claim 20, further comprising varying the frequency of the PLL to statistically decorrelate the plurality of samples during the initial calibration mode.

22. The method of claim 19, wherein sampling the one or more output clock signals comprises generating an I sample signal by sampling an in-phase (I) local oscillator signal and generating a Q sample signal by sampling a quadrature-phase (Q) local oscillator signal.

23. The method of claim 22, further comprising generating an I phase signal and a Q phase signal based on the tracking digital phase signal using a numerically controlled oscillator (NCO), wherein generating the phase difference signal comprises accumulating a plurality of cross-multiplications of a first complex signal and a complex conjugate of a second complex signal, wherein the first complex signal comprises the I phase signal and the Q phase signal, and wherein the second complex signal comprises the I sample signal and the Q sample signal.

24. The method of claim 19, further comprising generating a master digital phase signal using a master phase control circuit, and providing the phase adjustment to the PLL based also on the master digital phase signal.

25. A massive multiple-input multiple-output (MIMO) system comprising:

a plurality of frequency synthesizers configured to generate a plurality of local oscillator signals based on timing of a common reference clock signal, wherein a first frequency synthesizer of the plurality of frequency synthesizers comprises;

a phase-locked loop (PLL) configured to generate one or more local oscillator signals of the plurality of local oscillator signals;

a sampling circuit configured to generate a plurality of samples by sampling the one or more local oscillator signals based on timing of the common reference clock signal;

a phase difference calculation circuit configured to generate a phase difference signal based on the plurality of samples and a tracking digital phase signal representing the phase of the PLL; and

a phase adjustment control circuit configured to provide a phase adjustment to the PLL based on the phase difference signal.