Encoder resolution reduction

• US 9,979,412 B2
• Filed: 01/18/2013
• Issued: 05/22/2018
• Est. Priority Date: 01/18/2013
• Status: Active Grant

• Current Assignee: Otis Elevator Company (Otis Worldwide Corp.)
• Original Assignee: Otis Elevator Company (Otis Worldwide Corp.)
• Inventors: Kang, Keunmo, Culp, Slade, Bogli, Craig Drew, Veronesi, William A., Marvin, Daryl J.
• Primary Examiner(s): SALATA, ANTHONY J
• Application Number:
  US14/760,897
• Publication Number:
  US 20150365103A1
• Time in Patent Office: 1,950 Days
• Field of Search: 187247, 187391, 187393, 25023113, 25023114, 73 108, 73 111, 73 137, 73 141, 73 145, 702145, 702147, 702151, 324 7639, 324 7677, 324 7678, 324 7679, 324 7682, 324 90, 324144
• CPC Class Codes: B66B 1/3492 Position or motion detectors or driving means for the detector B66B1/40, B66B1/50 take precedence; length measuring G01B; speed measuring G01P
• CPC Class Codes: G01D 5/347 using displacement encoding scales
• CPC Class Codes: H03M 1/22 pattern-reading type
• CPC Class Codes: H03M 1/303 Circuits or methods for processing the quadrature signals
• CPC Class Codes: H03M 5/02 Conversion to or from representation by pulses
• CPC Class Codes: H03M 7/3059 Digital compression and data reduction techniques where the original information is represented by a subset or similar information, e.g. lossy compression

Abstract

One or more embodiments are directed to an encoder configured to output a signal, and a computing device configured to receive the signal from the encoder and generate a reduced resolution version of the signal, the computing device is configured to transmit the reduced resolution version of the signal to a recipient.

Claims

1. A method comprising:

receiving, by a device, two channels associated with an output of an encoder;

executing, by the device, a first algorithm to detect a direction of movement of an entity the encoder is applied to based on the two channels;

executing, by the device, a second algorithm to generate two channels with a reduced resolution relative to the two channels associated with the output of the encoder, the two channels with the reduced resolution comprising the detected direction of movement; and

outputting, by the device, the two channels with the reduced resolution.

2. The method of claim 1, wherein the second algorithm comprises a counter configured to output a pulse for each of the two channels with the reduced resolution based on having counted a number of input pulses in a corresponding one of the two channels associated with the output of the encoder.

3. The method of claim 1, wherein the first algorithm is configured to detect at least one of rising and falling edges in the two channels associated with the output of the encoder in detecting the direction of movement of the entity the encoder is applied to.

4. The method of claim 1, wherein the first algorithm is configured to detect voltage levels of the two channels associated with the output of the encoder in detecting the direction of movement of the entity the encoder is applied to.

5. The method of claim 1, wherein the entity the encoder is applied to comprises a rotating motor.

6. The method of claim 1, further comprising:

outputting, by the device, the two channels with the reduced resolution for receipt by an elevator rescue system.

14. The method of claim 1, wherein the device comprises:

a decoder component configured to receive inputs that are in quadrature with one another, determine a direction of the inputs, and generate a pulse responsive to a transition in either of the inputs;

a modulo counter component configured to be incremented responsive to the pulse when the direction of the inputs corresponds to a first direction and decremented responsive to the pulse when the direction of the inputs corresponds to a second direction; and

a quadrature output component configured to divide a count output by the modulo counter into a plurality of segments and generate a pair of quadrature output signals.

15. The method of claim 14, wherein the device further comprises:

a filter component configured to filter glitches associated with the inputs; and

a factory test component configured to selectively output as the inputs one of optical encoder inputs in quadrature with one another and simulated quadrature signals as a function of one or more test pins or test inputs.

16. The method of claim 15, wherein the decoder component, the modulo counter component, the quadrature output component, the filter component, and the factory test component are configured to be synchronized to one another via a clock, and wherein the factory test component is configured to generate the simulated quadrature signals based on a division of the clock.

7. A system comprising:

an encoder configured to output two channels; and

a computing device configured to;

receive the two channels output by the encoder,

detect a direction of movement of an entity the encoder is applied to based on the two channels,

generate two channels with a reduced resolution relative to the two channels associated with the output of the encoder, the two channels with the reduced resolution comprising the detected direction of movement, and

output the two channels with the reduced resolution.

8. The system of claim 7, wherein the computing device comprises a counter configured to output a pulse for each of the two channels with the reduced resolution based on having counted a number of input pulses in a corresponding one of the two channels output by the encoder.

9. The system of claim 7, wherein the computing device is configured to detect at least one of rising and falling edges in the two channels output by the encoder in detecting the direction of movement of the entity the encoder is applied to.

10. The system of claim 7, wherein the computing device is configured to detect voltage levels in the two channels output by the encoder in detecting the direction of movement of the entity the encoder is applied to.

11. The system of claim 7, wherein the computing device comprises at least one of:

a complex programmable logic device (CPLD), a field programmable gate array (FPGA), and a microprocessor/microcontroller.

12. The system of claim 7, wherein the encoder comprises a reflective encoder.

13. The system of claim 7, wherein the encoder and computing device are associated with at least one of an elevator and an elevator system.